registers and counters
DESCRIPTION
Registers and Counters. Discussion D8.1. Logic Design Fundamentals - 3. Registers Counters Shift Registers. A 1-Bit Register. Behavior. if rising_edge(CLK) then if LOAD = ‘1’ then Q0TRANSCRIPT
Registers and Counters
Discussion D8.1
Logic Design Fundamentals - 3
• Registers• Counters• Shift Registers
A 1-Bit Register
reg1Q0
!Q0
LOAD
INP0
CLK
if rising_edge(CLK) then if LOAD = ‘1’ then Q0 <= INP0; end if;end if;
Behavior
A 4-Bit Register
reg1Q0
!Q0
LOAD
INP0
reg1Q1
!Q1INP1
reg1Q2
!Q2INP2
reg1Q3
!Q3INP3
CLK
reg1Q0
!Q0
LOAD
INP0
CLK
q(n-1 downto 0)
clk clr
load
d(n-1 downto 0)
reg
library IEEE;use IEEE.std_logic_1164.all; entity reg is generic(width: positive); port ( d: in STD_LOGIC_VECTOR (width-1 downto 0); load: in STD_LOGIC; clr: in STD_LOGIC; clk: in STD_LOGIC; q: out STD_LOGIC_VECTOR (width-1 downto 0) );end reg;
A Generic Register
architecture reg_arch of reg isbegin process(clk, clr) begin if clr = '1' then for i in width-1 downto 0 loop q(i) <= '0'; end loop; elsif (clk'event and clk = '1') then if load = '1' then q <= d; end if; end if; end process; end reg_arch;
q(n-1 downto 0)
clk clr
load
d(n-1 downto 0)
reg
Infers a flip-flop for alloutputs (q)
entity regr is generic(width: positive; bit0: std_logic;
bit1: std_logic); port ( d: in STD_LOGIC_VECTOR (width-1 downto 0); load: in STD_LOGIC; reset: in STD_LOGIC; clk: in STD_LOGIC; q: out STD_LOGIC_VECTOR (width-1 downto 0) );end regr;
A Generic Registerwith an initial value of 0 - 3
architecture regr_arch of regr isbegin process(clk, reset) begin if reset = '1' then
q <= (others => '0'); q(0) <= bit0; q(1) <= bit1;
elsif (clk'event and clk = '1') then if load = '1' then q <= d; end if; end if; end process; end regr_arch;
A Generic Registerwith an initial value of 0 - 3
3-Bit Counter
if clr = '1' then count <= "000";elsif rising_edge(clk) then count <= count + 1;end if;
Q <= count;
Behavior
signal count: STD_LOGIC_VECTOR (2 downto 0);
count3clr
clkq(2 downto 0)
library IEEE;use IEEE.STD_LOGIC_1164.all;use IEEE.STD_LOGIC_unsigned.all;
entity count3 is port(
clk : in STD_LOGIC; clr : in STD_LOGIC; q : out STD_LOGIC_VECTOR(2 downto 0)
);end count3;
architecture count3 of count3 issignal count: STD_LOGIC_VECTOR(2 downto 0);begin
process(clr,clk)begin if clr = '1' then
count <= "000"; elsif clk'event and clk = '1' then
count <= count + 1; end if;end process;q <= count;
end count3;
count3.vhd
Asynchronous clear
Need signal becauseq can not be read
Signal count incrementson rising edge of clk
count3 Simulation
signal clk, cclk: std_logic;signal clkdiv: std_logic_vector(23 downto 0);begin
-- Divide the master clock (50Mhz) down to a lower frequency. process (mclk) begin
if mclk = '1' and mclk'event then clkdiv <= clkdiv + 1;end if;
end process;
clk <= clkdiv(0); -- mclk/2 = 25 MHz cclk <= clkdiv(17); -- mclk/218 = 190 Hz
Clock Dividermclk = 50 MHz master clock
4-Bit Shift Register
CLK
D Q
!Q CLK
D Q
!Q CLK
D Q
!Q CLK
D Q
!Q
data_in
CLK
Q0Q1Q2Q3
s(3) s(2) s(1) s(0)
if rising_edge(CLK) then for i in 0 to 2 loop
s(i) := s(i+1); end loop; s(3) := data_in;end if;
Behavior
library IEEE;use IEEE.STD_LOGIC_1164.all;
entity shift4 is port(
data_in : in STD_LOGIC; clk : in STD_LOGIC; clr : in STD_LOGIC; Q : out STD_LOGIC_VECTOR(3 downto 0)
);end shift4;
architecture shift4 of shift4 isbegin
process(clr,clk)variable s: STD_LOGIC_VECTOR(3 downto 0);begin if clr = '1' then
s := "0000"; elsif clk'event and clk = '1' then
for i in 0 to 2 loop s(i) := s(i+1);
end loop; s(3) := data_in;
end if; Q <= s;end process;
end shift4;
shift4.vhd
shift4 simulation
Ring Counter
CLK
D Q
!Q CLK
D Q
!Q CLK
D Q
!Q CLK
D Q
!Q
CLK
Q0Q1Q2Q3
if rising_edge(CLK) then for i in 0 to 2 loop
s(i) <= s(i+1); end loop; s(3) <= s(0);end if;
Behavior
s(3) s(2) s(1) s(0)
Note: Must use signals here
library IEEE;use IEEE.STD_LOGIC_1164.all;
entity ring4 is port(
clk : in STD_LOGIC; reset : in STD_LOGIC; Q : out STD_LOGIC_VECTOR(3 downto 0)
);end ring4;
architecture ring4 of ring4 issignal s: STD_LOGIC_VECTOR(3 downto 0);begin
process(reset,clk)begin if reset = '1' then
s <= "0001"; elsif clk'event and clk = '1' then
for i in 0 to 2 loop s(i) <= s(i+1);
end loop; s(3) <= s(0);
end if;end process;Q <= s;
end ring4;
ring4.vhd
Note: Must use signals here
ring4 simulation
CLK
D Q
!Q CLK
D Q
!Q CLK
D Q
!Q CLK
D Q
!Q
CLK
Q3 Q2 Q1 Q0
A Random Number Generator
if rising_edge(CLK) then for i in 0 to 2 loop
s(i) <= s(i+1); end loop; s(3) <= s(0) xor s(3);end if;
Behavior
s(3) s(2) s(1) s(0)
CLK
D Q
!Q CLK
D Q
!Q CLK
D Q
!Q CLK
D Q
!Q
CLK
Q3 Q2 Q1 Q0
Q3 Q2 Q1 Q00 0 0 1 11 0 0 0 81 1 0 0 C1 1 1 0 E1 1 1 1 F0 1 1 1 71 0 1 1 B0 1 0 1 5
Q3 Q2 Q1 Q01 0 1 0 A1 1 0 1 D0 1 1 0 60 0 1 1 31 0 0 1 90 1 0 0 40 0 1 0 20 0 0 1 1
library IEEE;use IEEE.STD_LOGIC_1164.all;
entity rand4 is port(
clk : in STD_LOGIC; reset : in STD_LOGIC; Q : out STD_LOGIC_VECTOR(3 downto 0)
);end rand4 ;
architecture rand4 of rand4 issignal s: STD_LOGIC_VECTOR(3 downto 0);begin
process(reset,clk)begin if reset = '1' then
s <= "0001"; elsif clk'event and clk = '1' then
for i in 0 to 2 loop s(i) <= s(i+1);
end loop; s(3) <= s(0) xor s(3);
end if;end process;Q <= s;
end rand4;
rand4.vhd
rand4 simulation
clock_pulse
inpdelay1
delay3
delay2
outp
cclk
inpdelay1
delay3
delay2
outp
inpdelay1
delay3
delay2
outp
library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;
entity clock_pulse isport (
inp, cclk, clr: in std_logic;outp: out std_logic);
end clock_pulse;
clock_pulse
inpdelay1
delay3
delay2
outp
cclk
inpdelay1
delay3
delay2
outp
inpdelay1
delay3
delay2
outp
architecture clock_pulse_arch of clock_pulse issignal delay1, delay2, delay3: std_logic;begin process(cclk, clr) begin if clr = '1' then delay1 <= '0';
delay2 <= '0'; delay3 <= '0';
elsif cclk'event and cclk='1' then delay1 <= inp; delay2 <= delay1; delay3 <= delay2;
end if; end process; outp <= delay1 and delay2 and (not delay3);end clock_pulse_arch;
inpdelay1
delay3
delay2
outp
cclk
inpdelay1
delay3
delay2
outp
inpdelay1
delay3
delay2
outp
clock_pulse
inpdelay1
delay3
delay2
outp
cclk
inpdelay1
delay3
delay2
outp
inpdelay1
delay3
delay2
outpclock_pulse