Registers, Counters, and Dividers - cvut. ?· Registers, Counters, and Dividers VHL code similarities…

Download Registers, Counters, and Dividers - cvut. ?· Registers, Counters, and Dividers VHL code similarities…

Post on 26-Jul-2018

212 views

Category:

Documents

0 download

Embed Size (px)

TRANSCRIPT

  • 6.11.2014

    1

    Computer System Structures

    cz:Struktury potaovch systm

    Lecturer: Richard usta

    VUT-FEL in Prague, CR subject A0B35SPS

    Version: 1.0

    Registers, Counters,

    and Dividers

    VHL code similarities and differences

  • 6.11.2014

    2

    SPS 3

    1 bit Register

    with Clear - Synchronous and Asynchronous

    SCLRN

    CLK

    D

    CLK

    Q

    CLRN

    ACLRN

    Power-up reset signal

    1

    1-bit register 0

    MUX21

    D

    '0' Q

    0

    1

    0 D

    ENA

    Q PRE

    CLR

    Q q~reg0

    SCLRN

    CLK

    D

    ACLRN

    SPS 4

    VHDL code of 1 bit register (1/3)

    library ieee; use ieee.std_logic_1164.all;

    entity reg is

    port( CLK, D, SCLRN, ACLRN : in std_logic;

    Q : out std_logic );

    end;

    architecture rtl of reg is

    constant QCLR:std_logic:='0';

    begin

    process (CLK, ACLRN)

    variable qv:std_logic;

    begin

    if ACLRN='0' then qv:=QCLR;

    elsif rising_edge(CLK) then

    if SCLRN='0' then qv:=QCLR; else qv:=D;

    end if;

    end if;

    Q

  • 6.11.2014

    3

    SPS 5

    VHDL code (2/3)

    library ieee;use ieee.std_logic_1164.all;

    entity reg is

    port( CLK, D, SCLRN, ACLRN : in std_logic;

    Q : out std_logic

    );

    end;

    architecture rtl of reg is

    constant QCLR:std_logic:='0';

    begin

    process (CLK, ACLRN) --- statements

    end process;

    end rtl;

    L:Libraries

    EP: entity-ports

    AD: architecture declarations

    EG: entity-generic -- generic ( list_of_generic_constants );

    -- begin +statements executed in compile type or simulation EX: entity-passive process

    AP: process concurrent statement

    ACS: architecture

    -concurrent statements -- next concurrent statements

    SPS 6

    process (CLK, ACLRN)

    variable qv:std_logic;

    begin

    if ACLRN='0' then qv:=QCLR;

    elsif rising_edge(CLK) then

    if SCLRN='0' then qv:=QCLR; else qv:=D;

    end if;

    end if;

    Q

  • 6.11.2014

    4

    SPS 7

    4 bit Register (1/3)

    with Clear - Synchronous and Asynchronous

    CLK

    D[3..0]

    CLK

    Q[3..0]

    CLRN

    ACLRN

    Power-up reset signal

    SCLRN

    1

    4-bit register 0

    MUX21

    D

    "0000" Q

    4

    4 4 4

    D Q PRE

    ENA

    CLR

    SEL DATAA

    DATAB OUT0

    MUX21

    4' h0 --

    qv~[3..0] SCLRN

    D[3..0] Q[3..0]

    qv[3..0]

    ACLRN

    CLK

    SPS 8

    4-bit register (2/3)

    EP: Entity-ports

    original: D : in std_logic;

    Q : out std_logic;

    new: D : in std_logic_vector(3 downto 0);

    Q : out std_logic_vector(3 downto 0);

    AD: Architecture declarations

    original: constant QCLR : std_logic:='0';

    new: constant QCLR : std_logic_vector(3 downto 0):="0000";

    AD: Process declarations

    original: variable qv:std_logic;

    new: variable qv:std_logic_vector(3 downto 0);

    changes in code

  • 6.11.2014

    5

    SPS 9

    4 bit register (3/3)

    library ieee;use ieee.std_logic_1164.all; entity reg4 is port( CLK, SCLRN, ACLRN : in std_logic;

    D : in std_logic_vector(3 downto 0); Q : out std_logic_vector(3 downto 0) ); end; architecture rtl of reg4 is

    constant QCLR:std_logic_vector(3 downto 0):="0000"; begin process (CLK, ACLRN) variable qv:std_logic_vector(3 downto 0); begin if ACLRN='0' then qv:=QCLR; elsif rising_edge(CLK) then if SCLRN='0' then qv:=QCLR; else qv:=D; end if; end if; Q

  • 6.11.2014

    6

    SPS 11

    How to create variable-width 0 vector

    Convert integer to variable 0 vector

    Add into L: Libraries numeric conversions

    use ieee.numeric_std.all;

    Convert integer literal to vector

    constant QCLR:std_logic_vector(WIDTH-1 downto 0)

    :=std_logic_vector ( to_unsigned(0,WIDTH) ); (see 5th lecture, slides from 58 to 60)

    Use others keyword

    constant QCLR:std_logic_vector(WIDTH-1 downto 0):=(others=>'0');

    OTHERS represents all possible values not already listed. In

    general, the meaning of

    (OTHERS => Value)

    is to set each bit of the destination operand to Value.

    SPS 12

    Variable-width Register (2/3)

    EG: Entity-generic

    generic( WIDTH:natural:=4 );

    EP: Entity-ports

    original: D : in std_logic_vector(3 downto 0);

    Q : out std_logic_vector(3 downto 0);

    new: D : in std_logic_vector(WIDTH-1 downto 0);

    Q : out std_logic_vector(WIDTH-1 downto 0);

    AD: Architecture declaration

    original: constant QCLR:std_logic_vector(3 downto 0):="0000"; new: constant QCLR:std_logic_vector(WIDTH-1 downto 0):=(others=>0);

    AD: Process declarations

    original: variable qv:std_logic_vector(3 downto 0);

    new: variable qv:std_logic_vector(WIDTH-1 downto 0);

    changes in code

  • 6.11.2014

    7

    SPS 13

    Variable-width Register (3/3)

    library ieee; use ieee.std_logic_1164.all;

    entity reg_width is

    generic( WIDTH:natural:=4 );

    port( CLK, SCLRN, ACLRN : in std_logic;

    D : in std_logic_vector(WIDTH-1 downto 0);

    Q : out std_logic_vector(WIDTH-1 downto 0) );

    end;

    architecture rtl of reg_width is

    constant QCLR:std_logic_vector(WIDTH-1 downto 0):=( others=>'0' );

    begin

    process (CLK, ACLRN)

    variable qv:std_logic_vector( WIDTH-1 downto 0 );

    begin

    if ACLRN='0' then qv:=QCLR;

    elsif rising_edge(CLK) then

    if SCLRN='0' then qv:=QCLR; else qv:=D;

    end if;

    end if;

    Q

  • 6.11.2014

    8

    SPS 15

    Circular Variable-width Shift Register (2/3)

    EP: Entity-ports

    change: SCLRN input was renamed to SLOAD

    PS: process-synchronous part

    original: if SCLRN='0' then

    qv:=QCLR;

    else qv:=D;

    end if;

    new: if SLOAD='0' then

    qv:=qv( WIDTH-2 downto 0) & qv(WIDTH-1);

    else qv:=D;

    end if;

    changes in code

    SPS 16

    Circular Variable-width Shift Register(3/3)

    library ieee; use ieee.std_logic_1164.all;

    entity reg_width is

    generic( WIDTH:natural:=4 );

    port( CLK, SLOAD, ACLRN : in std_logic;

    D : in std_logic_vector(WIDTH-1 downto 0);

    Q : out std_logic_vector(WIDTH-1 downto 0) );

    end;

    architecture rtl of reg_width is

    constant QCLR:std_logic_vector(WIDTH-1 downto 0):=( others=>'0' );

    begin

    process (CLK, ACLRN)

    variable qv:std_logic_vector( WIDTH-1 downto 0 );

    begin

    if ACLRN='0' then qv:=QCLR;

    elsif rising_edge(CLK) then

    if SLOAD='0' then qv:=qv(WIDTH-2 downto 0) & qv(WIDTH-1); else qv:=D;

    end if;

    end if;

    Q

  • 6.11.2014

    9

    SPS 17

    How to initialize variable-width shift

    Problem: Set shift after power up to a non zero state.

    Initial state=1 can be again accomplished by converting integer literal, but what about

    states with 1 only in main scale bit?

    Create initialization by association list with others keyword.

    constant QCLR:std_logic_vector(WIDTH-1 downto 0)

    := (0=>'1', others=>'0'); -- 1 only in QCLR(0)

    constant QCLR1:std_logic_vector(WIDTH-1 downto 0)

    := (WIDTH-1=>'1', others=>'0'); -- 1 only in QCLR(WIDTH-1)

    constant QCLR2:std_logic_vector(WIDTH-1 downto 0)

    := (WIDTH-1=>'0', 1=>'0', others=>'1'); -- 0 in QCLR(WIDTH-1) and QCLR(1)

    Association lists => provide the mapping between formal or local generics, ports, or

    subprogram parameter names and local or actual names or expressions.

    association_list ::= association_element { , association_element }

    association_element ::= [formal_part =>] actual_part

    (for details, see VHDL Reference Manual, page 4-31)

    SPS 18

    Variable Counter (1/3)

    CLK

    D[W-1..0]

    CLK

    Q[W-1..0]

    CLRN

    ACLRN

    Power-up reset signal

    SCLRN

    1

    1-bit register 0

    0 Q

    W

    W W

    W

    +1

    http://home.dei.polimi.it/sami/VHDL_reference_manual.pdfhttp://home.dei.polimi.it/sami/VHDL_reference_manual.pdfhttp://home.dei.polimi.it/sami/VHDL_reference_manual.pdf

  • 6.11.2014

    10

    SPS 19

    Counter definition

    1. Counters are typically defined by specifying

    a width in bits

    2. Counters send their states to outputs

    => Avoid integers requiring conversions. Use type unsigned

    or signed from library ieee.numeric_std.all; for counting

    variable, e.g.

    variable qv:unsigned(WIDTH-1 downto 0);

    binary counter can be incremented by

    qv:=qv+1; -- because