flip flops, counters & registers
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Flip flops, counters & registers
Flip flops, counters & registers
Flip flops
Flip flopsIntroductionMemory ElementsPulse-Triggered LatchS-R LatchGated S-R LatchGated D LatchEdge-Triggered Flip-flopsS-R Flip-flopD Flip-flopJ-K Flip-flopT Flip-flopAsynchronous Inputs
4IntroductionA sequential circuit consists of a feedback path, and employs some memory elements.
Combinational logic
Memory elements
Combinational outputs Memory outputs External inputs
Sequential circuit = Combinational logic + Memory Elements
IntroductionThere are two types of sequential circuits:synchronous: outputs change only at specific timeasynchronous: outputs change at any timeMultivibrator: a class of sequential circuits. They can be:bistable (2 stable states)monostable or one-shot (1 stable state)astable (no stable state)Bistable logic devices: latches and flip-flops.Latches and flip-flops differ in the method used for changing their state.
Sequential CircuitsCombinationalCircuitMemoryElements
InputsOutputsAsynchronous
SynchronousCombinationalCircuitFlip-flops
InputsOutputs
Clock
Memory ElementsMemory element: a device which can remember value indefinitely, or change value on command from its inputs.Characteristic table:
command
Memory element
stored value
QQ(t): current stateQ(t+1) or Q+: next state
Memory ElementsMemory element with clock. Flip-flops are memory elements that change state on clock signals.Clock is usually a square wave.command
Memory element
stored value
Q
clock
Positive edgesNegative edges
Positive pulses
Memory ElementsTwo types of triggering/activation:pulse-triggerededge-triggeredPulse-triggeredlatchesON = 1, OFF = 0Edge-triggeredflip-flopspositive edge-triggered (ON = from 0 to 1; OFF = other time)negative edge-triggered (ON = from 1 to 0; OFF = other time)
S-R LatchComplementary outputs: Q and Q'.When Q is HIGH, the latch is in SET state.When Q is LOW, the latch is in RESET state.For active-HIGH input S-R latch (also known as NOR gate latch),R=HIGH (and S=LOW) a RESET stateS=HIGH (and R=LOW) a SET stateboth inputs LOW a no changeboth inputs HIGH a Q and Q' both LOW (invalid)!
11 / 60LatchesSR Latch
S R Q0QQ0 0 0
010001
Q = Q0Initial Value
12 / 60LatchesSR Latch
S R Q0QQ0 0 0010 0 1
100010
Q = Q0Q = Q0
13 / 60LatchesSR Latch
S R Q0QQ0 0 0010 0 1100 1 00
01101
Q = 0
Q = Q0
14 / 60LatchesSR Latch
S R Q0QQ0 0 0010 0 1100 1 0010 1 1
101001
Q = 0
Q = Q0Q = 0
15 / 60LatchesSR Latch
S R Q0QQ0 0 0010 0 1100 1 0010 1 1011 0 0
010110
Q = 0
Q = Q0Q = 1
16 / 60LatchesSR Latch
S R Q0QQ0 0 0010 0 1100 1 0010 1 1011 0 0101 0 1
100110
Q = 0
Q = Q0Q = 1
Q = 1
17 / 60LatchesSR Latch
S R Q0QQ0 0 0010 0 1100 1 0010 1 1011 0 0101 0 1101 1 0
011100
Q = 0
Q = Q0Q = 1
Q = Q
0
18 / 60LatchesSR Latch
S R Q0QQ0 0 0010 0 1100 1 0010 1 1011 0 0101 0 1101 1 0001 1 1
101100
Q = 0
Q = Q0Q = 1
Q = Q
0Q = Q
19 / 60LatchesSR Latch
S RQ0 0Q00 101 011 1Q=Q=0
No changeResetSetInvalid
S RQ0 0Q=Q=10 111 001 1Q0
InvalidSetResetNo change
20 / 60LatchesSR Latch
S RQ0 0Q00 101 011 1Q=Q=0
No changeResetSetInvalid S RQ0 0Q=Q=10 111 001 1Q0
InvalidSetResetNo change
21 / 60Controlled LatchesSR Latch with Control InputC S RQ0 x xQ01 0 0Q01 0 101 1 011 1 1Q=Q
No changeNo changeResetSetInvalid
22 / 60Controlled LatchesD Latch (D = Data)C DQ0 xQ01 001 11
No changeResetSet
CTiming DiagramD
Q
t
Output may change
23 / 60Controlled LatchesD Latch (D = Data)C DQ0 xQ01 001 11
No changeResetSet
CTiming DiagramD
Q
Output may change
Latch Circuits: Not SuitableLatch circuits are not suitable in synchronous logic circuits.When the enable signal is active, the excitation inputs are gated directly to the output Q. Thus, any change in the excitation input immediately causes a change in the latch output.The problem is solved by using a special timing control signal called a clock to restrict the times at which the states of the memory elements may change.This leads us to the edge-triggered memory elements called flip-flops.
25 / 60Flip-FlopsControlled latches are level-triggered
Flip-Flops are edge-triggered
C
CLKPositive Edge
CLKNegative Edge
26 / 60Flip-FlopsMaster-Slave D Flip-Flop
D Latch (Master)D
CQ D Latch (Slave)D
CQ
QDCLK
CLKDQMaster
QSlave
Looks like it is negative edge-triggered
MasterSlave
27 / 60Flip-FlopsEdge-Triggered D Flip-Flop
D
Q
Q
D
Q
Q
Positive EdgeNegative Edge
28 / 60Flip-FlopsJK Flip-Flop
J
Q
Q
KD = JQ + KQ
29 / 60Flip-FlopsT Flip-FlopD = TQ + TQ = T Q
J
Q
Q
K
T
D
Q
Q
T
D = JQ + KQ
T
Q
Q
30 / 60Flip-Flop Characteristic Tables
D
Q
Q
DQ(t+1)0011
ResetSetJKQ(t+1)00Q(t)01010111Q(t)
No changeResetSetToggle
J
Q
Q
K
T
Q
Q
TQ(t+1)0Q(t)1Q(t)
No changeToggle
31 / 60Flip-Flop Characteristic Equations
D
Q
Q
DQ(t+1)0011
Q(t+1) = DJKQ(t+1)00Q(t)01010111Q(t)
Q(t+1) = JQ + KQ
J
Q
Q
K
T
Q
Q
TQ(t+1)0Q(t)1Q(t)
Q(t+1) = T Q
32 / 60Flip-Flop Characteristic EquationsAnalysis / Derivation
J
Q
Q
KJKQ(t)Q(t+1)00000011010011100101110111
No change
Reset
Set
Toggle
33 / 60Flip-Flop Characteristic EquationsAnalysis / Derivation
J
Q
Q
KJKQ(t)Q(t+1)0000001101000110100101110111
No change
Reset
Set
Toggle
34 / 60Flip-Flop Characteristic EquationsAnalysis / Derivation
J
Q
Q
KJKQ(t)Q(t+1)000000110100011010011011110111
No change
Reset
Set
Toggle
35 / 60Flip-Flop Characteristic EquationsAnalysis / Derivation
J
Q
Q
KJKQ(t)Q(t+1)00000011010001101001101111011110
No change
Reset
Set
Toggle
36 / 60Flip-Flop Characteristic EquationsAnalysis / Derivation
J
Q
Q
KJKQ(t)Q(t+1)00000011010001101001101111011110
K0100J1101Q
Q(t+1) = JQ + KQ
37 / 60Flip-Flops with Direct InputsAsynchronous Reset
D
Q
Q
R
Reset
RDCLKQ(t+1)0xx0
38 / 60Flip-Flops with Direct InputsAsynchronous Reset
D
Q
Q
R
Reset
RDCLKQ(t+1)0xx0100111
39 / 60Flip-Flops with Direct InputsAsynchronous Preset and ClearPRCLRDCLKQ(t+1)10xx0
D
Q
Q
CLR
Reset
PR
Preset
40 / 60Flip-Flops with Direct InputsAsynchronous Preset and ClearPRCLRDCLKQ(t+1)10xx001xx1
D
Q
Q
CLR
Reset
PR
Preset
41 / 60Flip-Flops with Direct InputsAsynchronous Preset and ClearPRCLRDCLKQ(t+1)10xx001xx111001111
D
Q
Q
CLR
Reset
PR
Preset
42 / 60Analysis of Clocked Sequential CircuitsThe StateState = Values of all Flip-Flops
Example A B = 0 0
43 / 60Analysis of Clocked Sequential CircuitsState Equations
A(t+1) = DA = A(t) x(t)+B(t) x(t) = A x + B xB(t+1) = DB = A(t) x(t) = A x y(t) = [A(t)+ B(t)] x(t) = (A + B) x
44 / 60Analysis of Clocked Sequential CircuitsState Table (Transition Table)
A(t+1) = A x + B xB(t+1) = A x y(t) = (A + B) xPresent StateInputNext StateOutputABxABy000001010011100101110111
t+1tt
0 0 00 1 00 0 11 1 00 0 11 0 00 0 11 0 0
45 / 60Analysis of Clocked Sequential CircuitsState Table (Transition Table)
A(t+1) = A x + B xB(t+1) = A x y(t) = (A + B) xPresent StateNext StateOutputx = 0x = 1x = 0x = 1ABABAByy00000100010011101000101011001010
t+1tt
46 / 60Analysis of Clocked Sequential CircuitsState Diagram
0 0
1 0
0 1
1 1
0/00/11/01/01/01/00/10/1AB
input/output
Present StateNext StateOutputx = 0x = 1x = 0x = 1ABABAByy00000100010011101000101011001010
47 / 60Analysis of Clocked Sequential CircuitsD Flip-FlopsExample:
D
Q
Q
x
CLKyAPresent StateInputNext StateAxyA000001010011100101110111
0110100101
00,1100,1101,1001,10A(t+1) = DA = A x y
48 / 60Analysis of Clocked Sequential CircuitsJK Flip-FlopsExample:
JA = BKA = B xJB = xKB = A xA(t+1) = JA QA + KA QA = AB + AB + AxB(t+1) = JB QB + KB QB = Bx + ABx + ABxPresent StateI/PNext StateFlip-FlopInputsABxABJAKAJBKB00000101001