Counters Mano & Kime Sections 5-4, 5-5. Counters Ripple Counter Synchronous Binary Counters –Design with D Flip-Flops –Design with J-K Flip-Flops Counters

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  • CountersMano & KimeSections 5-4, 5-5

  • CountersRipple CounterSynchronous Binary CountersDesign with D Flip-FlopsDesign with J-K Flip-FlopsCounters in VHDL

  • Counters ---

  • A 4-bit Ripple CounterRecall...Less SignificantBit output is Clockfor Next Significant Bit!(Clock - active low)

  • J-K Flip-Flop from a D Flip-FlopDQ = J & !Q # !K & QDQ = QDQ = 0DQ =!Q # Q = 1DQ = !Q

  • CountersRipple CounterSynchronous Binary CountersDesign with D Flip-FlopsDesign with J-K Flip-FlopsCounters in VHDL

  • Divide-by-8 Counter

  • Divide-by-8 CounterQ2Q1 Q000011110011111Q2.DQ2.D = !Q2 & Q1 & Q0 # Q2 & !Q1 # Q2 & !Q0

  • Divide-by-8 CounterQ2Q1 Q000011110011111Q1.DQ1.D = !Q1 & Q0 # Q1 & !Q0

  • Divide-by-8 CounterQ2Q1 Q000011110011111Q0.DQ0.D = ! Q0

  • CUPL SimulationOutput File

  • 3-Bit Down Counter

  • 3-Bit Down CounterQ2Q1 Q000011110011111Q2.DQ2.D = !Q2 & !Q1 & !Q0 # Q2 & Q1 # Q2 & Q0

  • 3-Bit Down CounterQ2Q1 Q000011110011111Q1.DQ1.D = !Q1 & !Q0 # Q1 & Q0

  • 3-Bit Down CounterQ2Q1 Q000011110011111Q0.DQ0.D = ! Q0

  • Up-Down CounterUp-DownCounterQ0

    Q1

    Q2clockUDUD = 0: count upUD = 1: count down

  • Up-Down Counter1 0 0 0 1 1 11 0 0 1 0 0 01 0 1 0 0 0 11 0 1 1 0 1 01 1 0 0 0 1 11 1 0 1 1 0 01 1 1 0 1 0 11 1 1 1 1 1 0

    UD Q2 Q1 Q0 Q2.D Q1.D Q0.D0 0 0 0 0 0 10 0 0 1 0 1 00 0 1 0 0 1 10 0 1 1 1 0 00 1 0 0 1 0 10 1 0 1 1 1 00 1 1 0 1 1 10 1 1 1 0 0 0

    UD Q2 Q1 Q0 Q2.D Q1.D Q0.DUp-CounterDown-Counter

  • Up-Down CounterUD Q2 Q1 Q00001111000011110Make Karnaugh maps for Q2.D, Q1.D, and Q0.D

  • CountersRipple CounterSynchronous Binary CountersDesign with D Flip-FlopsDesign with J-K Flip-FlopsCounters in VHDL

  • J-K Flip Flop Design of a Binary Up Counter Synchronous Binary Counters

  • J-K Flip Flop Design of a Binary Up Counter Synchronous Binary Counters

  • J-K Flip Flop Design of a Binary Up Counter Synchronous Binary Counters

  • J-K Flip Flop Design of a Binary Up Counter Synchronous Binary Counters

  • 4 - Bit CounterLogic Diagram

  • CountersRipple CounterSynchronous Binary CountersDesign with D Flip-FlopsDesign with J-K Flip-FlopsCounters in VHDL

  • 4-Bit Binary Counter with Reset