lec15 intro to computer engineering by hsien-hsin sean lee georgia tech -- registers, flip-flops,...
TRANSCRIPT
ECE2030 Introduction to Computer Engineering
Lecture 15: Registers, Toggle Cells, Counters
Prof. Hsien-Hsin Sean LeeProf. Hsien-Hsin Sean LeeSchool of Electrical and Computer EngineeringSchool of Electrical and Computer EngineeringGeorgia TechGeorgia Tech
2
4-bit Register• Register is the most fundamental storage,
e.g.– x86 ISA has 8 general purpose registers – MIPS ISA has 32 general purpose registers
• Each 1-bit Flip-flop is a single bit register• Cascade 4 of 1-bit FFs = A 4-bit Register
in0in0
1-bit D1-bit DFlip FlopFlip Flop
11
out0out0
22
in1in1
1-bit D1-bit DFlip FlopFlip Flop
out1out1
in2in2
1-bit D1-bit DFlip FlopFlip Flop
out2out2
in3in3
1-bit D1-bit DFlip FlopFlip Flop
out3out3
3
Read/Write Control a Register• Read: Retrieve data stored inside a flip-flop• Write: Update with a new input data into a flip-flop• Given 1 and 2 are continuous clock signals
OutputOutput1-bit D1-bit DFlip FlopFlip Flop
11 22
In In READREAD mode mode
OutputOutput1-bit D1-bit DFlip FlopFlip Flop
11 22
InputInput
In In WriteWrite mode mode
4
Read/Write Control a Register
OutputOutput1-bit D1-bit DFlip FlopFlip Flop
11 22InputInput
R/W
5
Another Read/Write Control of a Register
OutputOutput1-bit D1-bit DFlip FlopFlip Flop
11 22
InputInput
R/WClock Gating
6
4-bit Register with Parallel LoadQ3Q3
1 2
D Q
D3D3
R / W
Q2Q2
1 2
D Q
D2D2
Q1Q1
1 2
D Q
D1D1
Q0Q0
1 2
D Q
D0D0
7
Logical Shift Register
1 2
D Q
1 2
D Q
1 2
D Q
1 2
D Q
A3 A2 A1 A0
1 2 1 2 1 2 1 2
Right Shift
8
Arithmetic Shift Register
1 2
D Q
1 2
D Q
1 2
D Q
1 2
D Q
A3 A2 A1 A0
1 2 1 2 1 2 1 2
Right Shift
9
Bidirectional Shift Register with Load (1-bit shown)
4-to-1 Mux11 10 01 00s1
s0
1 2
D Q
1 2
D Q
1 2
D Q Q i+1 Q i Q i-1
Di
00: No shift01: Shift Left10: Shift Right11: Load from Di
10
Serial Transfer
D Q D Q D Q D QShift Out(SO)
Shift In(SI)
Clock
11
Serial Shift Register
D Q D Q D Q D QShift Out(SO)
(SI)
Clock
Clear
SR4SI SO
ClockClear
12
Design a Serial Adder (yet another adder)
SR4 ASI SO
ClockClear
SR4 BSI SO
ClockClear
++A
B
S
CoCi
D QClear
A A+B
(1) Clear SRs (2) B 0111 (4 clks)(3) B=0111 A=0000(4) B=1011 A=1000(5) B=1101 A=1100(6) B=0110 A=1110(7) B=0011 A=0111(8) B=0001 A=0011(9) B=0000 A=1001(10)B=0000 A=0100(11)B=0000 A=1010
Ex: 0111 (A)+ 0011 (B)----------------
Input
13
Toggle Flip-Flop (Toggle Cell)• Upon every clock, the output result is toggled
D1D1 Q1Q1 D2D2 Q2Q2
D1D1
D1D1
Q1=D2Q1=D2
Q2Q2
EnEn EnEn
EnEn
Transparent latch
Transparent latch
14
Toggle Flip-Flop
D1D1 Q1Q1 D2D2 Q2Q2
11 22
Toggle Enable Bit(or TE bit)
Toggle bit controls to toggle (T=1) or not to toggle (T=0)Toggle bit controls to toggle (T=1) or not to toggle (T=0)
Transparent latch
Transparent latch
15
Toggle F/F with Clear bit
Clear Toggle Enable
Present Output
Next Output
0 X X 0
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
D1D1 Q1Q1 D2D2 Q2Q2
11 22
TE BitOutputOutput
ClearTransparent
latchTransparent
latch
Note that output changes every clock cycle (e.g.rising edge or falling edge)
16
Toggle F/F Symbol
TE Q
CLR
11 22
Clear TE Present Q Next Q0 X X 0
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
17
Counters• A register counts up or down per clock period
– Count in binary – Could be preset: (with parallel loads)
• Types of counters– Ripple counter– Synchronous counter– Mod-n counter– Up/down counter– BCD counter– Gray code counter– Ring counter a 1 moves in a ring from one F/F to
the next– Johnson counter (or twisted ring count.) The
MSB is inversed and passed to the LSB)
18
2-bit Ripple CounterTE Q
CLR
11 22
TE Q
CLR
O0O0 O1O1
Count Enable
11
O0O0
19
2-bit Ripple CounterTE Q
CLR
11 22
TE Q
CLR
O0O0 O1O1
Count Enable
11
O0O0
O1O1
0
0
1
0
0
1
1
1
0
0
1
0
0
1
20
4-bit Ripple CounterCount Enable
11
O0O0
O1O1
TE Q
CLR
11 22
TE Q
CLR
O0O0 O1O1
TE Q
CLR
O2O2
TE Q
CLR
O3O3
O2O2
O3O3
21
4-bit Synchronous CounterCount Enable
TE Q
CLR
1122
O0O0
TE Q
CLR
O1O1
TE Q
CLR
O2O2
TE Q
CLR
O3O3
Clocks are applied to Clocks are applied to the inputs of all the F/Fthe inputs of all the F/F
11O0O0
=TE1=TE1O1O1
O2O2
O4O4
22
Modulo-N (or Divide-by-N) Counter
• Mod-N– Count from 0 to N-1– Then reset and start over
CLRCLR
CECE
O3O3 O2O2 O1O1 O0O0
11
224-bit Counter4-bit Counter
MOD-10 counterMOD-10 counter(a BCD Counter)(a BCD Counter)
CLR
Terminal Count (TC)
23
Cascaded BCD Counter
CLRCLRCECE
O3O3 O2O2 O1O1 O0O0
11
22Mod-10 Mod-10 CounterCounter
TCTCCLRCLRCECE
O3O3 O2O2 O1O1 O0O0
11
22Mod-10 Mod-10 CounterCounter
TCTC
O7O7 O6O6 O5O5 O4O4 O3O3 O2O2 O1O1 O0O0
Vdd