1

Registers & Counters

Mantıksal Tasarım – BBM231M. Önder Efe

onderefe@cs.hacettepe.edu.tr

2

Registers• Registers are clocked sequential circuits• A register is a group of flip-flops– Each flip-flop capable of storing one bit of information– An n-bit register • consists of n flip-flops• capable of storing n bits of information

– besides flip-flops, a register usually contains combinational logic to perform some simple tasks

– In summary• flip-flops to hold information• combinational logic to control the state transition

3

Counters• A counter is essentially a register that goes through a predetermined

sequence of states• “Counting sequence”

RegisterFF0 FF1 FFn-1

Combinational logic

4

Uses of Registers and Counters• Registers are useful for storing and manipulating

information– internal registers in microprocessors to manipulate data

• Counters are extensively used in control logic– PC (program counter) in microprocessors

5

4-bit RegisterREG

Q3

Q2

Q1

Q0

D3

D2

D1

D0

clear

D Q

clock

CR

D Q

CR

D Q

CR

D Q

CR

clear

D0

D1

D2

D3

Q0

Q1

Q2

Q3

FD16CE

16 16D[15:0] Q[15:0]

CE

C CLR

Verilog Code of FD16CEalways @ (posedge C or posedge CLR)

beginif (CLR)

Q <= 4’b0000;else

beginif (CE)

Q <= D;end

end

7

Register with Parallel LoadLoad

D Q

CR

Q0

D Q

CR

Q1

D Q

CR

Q2

D Q

CR

Q3

clockclear

D1

D2

D3

D0

8

Register Transfer 1/2

R1 R2

n

load

clock

load

clock

R2 R1

R1 010…10 110…11

010…10R2

9

Register Transfer 2/2

R1 R1 + R2

clock

R1 R2

n

n-bit adder

n

load

10

Shift Registers• A register capable of shifting its content in one or both

directions – Flip-flops in cascade

serial input

serial outputD Q

C

SID Q

C

D Q

C

D Q

C

SO

clock

• The current of n-bit shift register state can be transferred in n clock cycles

11

Serial Mode• A digital system is said to operate in serial mode when

information is transferred and manipulated one bit a time.

shift register A shift register BSOSI SI SO

clk clkclockshiftcontrol

clock

shift control

clk

T1 T2 T3 T4

12

Serial Transfer• Suppose we have two 4-bit shift registers

11011101After T4

After T3

After T2

After T1

01001101initial value

Shift register BShift register ATiming pulse

B A

clock

shift control

clk

T1 T2 T3 T4

A Bclk clk

clockshiftcontrol

13

Serial Addition• In digital computers, operations are usually executed in

parallel, since it is faster• Serial mode is sometimes preferred since it requires

less equipment

shift register A

shift register B

SI

FAab

C_in

S

C

DQ

C

SO

SO

SIserialinput

clockshiftcontrol

clear

serialoutput

Example: Serial Addition

14

• A and B are 2-bit shift registers

clock

00 10

00 00

shift control

SR-A

SR-B

C_in

01

01

15

Universal Shift Register

• Capabilities:1. A “clear” control to set the register to 0.2. A “clock” input3. A “shift-right” control4. A “shift-left” control5. n input lines & a “parallel-load” control6. n parallel output lines

16

4-Bit Universal Shift Register

D

Q

CD

Q

CD

Q

CD

QC

A0A1A2A3

parallel outputs

clearclk

41MUX

0123

41MUX

0123

41MUX

0123

41MUX

0123

s1

s0

serialinput for shift-right

serial input for shift-left

parallel inputs

Verilog Code – v1// Behavioral description of a 4-bit universal shift register// Fig. 6.7 and Table 6.3module Shift_Register_4_beh ( // V2001, 2005output reg [3: 0] A_par, // Register outputinput [3: 0] I_par, // Parallel inputinput s1, s0, // Select inputsMSB_in, LSB_in, // Serial inputsCLK, Clear_b // Clock and Clearalways @ ( posedge CLK, negedge Clear_b) // V2001, 2005

if (Clear_b == 0) A_par <= 4’b0000;else

case ({s1, s0})2'b00: A_par <= A_par; // No change2'b01: A_par <= {MSB_in, A_par[3: 1]}; // Shift right2'b10: A_par <= {A_par[2: 0], LSB_in}; // Shift left2'b11: A_par <= I_par; // Parallel load of input

endcaseendmodule

17

Verilog Code – v2// Behavioral description of a 4-bit universal shift register// Fig. 6.7 and Table 6.3module Shift_Register_4_beh ( // V2001, 2005output reg [3: 0] A_par, // Register outputinput [3: 0] I_par, // Parallel inputinput s1, s0, // Select inputsMSB_in, LSB_in, // Serial inputsCLK, Clear_b // Clock and Clearalways @ ( posedge CLK, negedge Clear_b) // V2001, 2005

if (Clear_b == 0) A_par <= 4’b0000;else

case ({s1, s0})// 2'b00: A_par <= A_par; // No change2'b01: A_par <= {MSB_in, A_par [3: 1]}; // Shift right2'b10: A_par <= {A_par [2: 0], LSB_in}; // Shift left2'b11: A_par <= I_par; // Parallel load of input

endcaseendmodule

18

19

Universal Shift Register

Mode Control

Register operations1 s0

0 0 No change

0 1 Shift right

1 0 Shift left

1 1 Parallel load

20

Counters• registers that go through a prescribed sequence

of states upon the application of input pulses– input pulses are usually clock pulses

• Example: n-bit binary counter– count in binary from 0 to 2n-1

• Classification1. Synchronous counters• flip-flops receive the same common clock as the pulse

2. Ripple counters• flip-flop output transition serves as the pulse to trigger

other flip-flops

21

Binary Ripple Counter

0 0 0 01 0 0 12 0 1 03 0 1 14 1 0 05 1 0 16 1 1 07 1 1 10 0 0 0

3-bit binary ripple counter

• Idea:– to connect the output of one flip-flop to

the C input of the next high-order flip-flop• We need “complementing” flip-flops– We can use T flip-flops to obtain

complementing flip-flops or– JK flip-flops with its inputs are tied

together or– D flip-flops with complement output

connected to the D input.

22

4-bit Binary Ripple CounterT Q

CR

A0

T Q

CR

A1

T Q

CR

A2

T Q

CR

A3

clear

count

logic-1

D Q

CR

A0

D Q

CR

A1

D Q

CR

A2

D Q

CR

A3

clear

count0 0 0 0 01 0 0 0 12 0 0 1 03 0 0 1 14 0 1 0 05 0 1 0 16 0 1 1 07 0 1 1 18 1 0 0 09 1 0 0 110 1 0 1 011 1 0 1 112 1 1 0 013 1 1 0 114 1 1 1 015 1 1 1 10 0 0 0 0

23

4-bit Binary Ripple CounterT Q

CR

A0

T Q

CR

A1

T Q

CR

A2

T Q

CR

A3

clear

count

logic-1

24

Synchronous Counters• There is a common clock– that triggers all flip-flops simultaneously– If T = 0 or J = K = 0 the flip-flop

does not change state.– If T = 1 or J = K = 1 the flip-flop

does change state.• Design procedure is so simple– no need for going through sequential

logic design process– A0 is always complemented

– A1 is complemented when A0 = 1

– A2 is complemented when A0 = 1 and A1 = 1 – so on

0 0 0 0

1 0 0 1

2 0 1 0

3 0 1 1

4 1 0 0

5 1 0 1

6 1 1 0

7 1 1 1

0 0 0 0

25

4-bit Binary Synchronous CounterJ Q

CA0

J QC

A1

J QC

A2

J QC

A3

K

K

K

K

clock

Count_enable

to next stage

Polarity of theclock is notessential

Timing of Synchronous Counters

26

A0

clock

A3

A1

A2

Timing of Ripple Counters

2727

A0

clock

A3

A1

A2

28

Up-Down Binary Counter

• When counting downward– the least significant bit is always

complemented (with each clock pulse)

– A bit in any other position is complemented if all lower significant bits are equal to 0.

– For example: 0 1 0 0 • Next state:

– For example: 1 1 0 0• Next state:

0 0 0 0

7 1 1 1

6 1 1 0

5 1 0 1

4 1 0 0

3 0 1 1

2 0 1 0

1 0 0 1

0 0 0 0

29

Up-Down Binary Counter

• The circuit

T Q

C

A0

T Q

C

A1

T Q

C

A2

Cclock

up

down

30

Binary Counter with Parallel LoadJ Q

CA0

J QC

A1

J QC

A2

K

K

K

clock

clear

countloadD0

D1

D2

carryoutput

31

Binary Counter with Parallel Load

clear clock load Count Function

0 X X X clear to 0

1 1 X load inputs

1 0 1 count up

1 0 0 no change

Function Table

32

Other Counters• Ring Counter– A ring counter is a circular shift register with only one flip-

flop being set at any particular time, all others are cleared.

shift right T0 T1 T2 T3

initial value1000

• Usage– Timing signals control the sequence of operations in a digital system

33

Ring Counter• Sequence of timing signals

clock

T0

T1

T2

T3

34

Ring Counter

• To generate 2n timing signals, – we need a shift register with ? flip-flops

• or, we can construct the ring counter with a binary counter and a decoder

2x4 decoder

T0 T1 T2 T3

2-bit countercount

Cost:• 2 flip-flops• 2-to-4 line decoderCost in general case: • n flip-flops• n-to-2n line decoder

• 2n n-input AND gates• n NOT gates

35

Johnson Counter• A k-bit ring counter can generate k

distinguishable states• The number of states can be doubled if the shift

register is connected as a switch-tail ring counter

clock

D Q

C

D Q

C

D Q

C

D Q

C

X

X’

Y

Y’

Z

Z’

T

T’

36

Johnson Counter• Count sequence and required decoding

S7 = Z’T

S6 = Y’Z

S5 = X’Y

S4 = XT

S3 = ZT’

S2 = YZ’

S1 = XY’

S0 = X’T’0000

8

7

6

5

4

3

2

1

TZYX OutputFlip-flop outputssequence number

0001

0011

0111

1111

1110

1100

1000

37

Johnson Counter• Decoding circuit

S0 S1 S2 S3 S4 S5 S6 S7

clock

D Q

C

D Q

C

D Q

C

D Q

C

X Y Z T

38

Unused States in Counters• 4-bit Johnson counter

0000 1000 1100

1110

111101110011

0001

0010 1001 0100

1010

110101101011

0101

39

Correction

0000 1000 1100

1110

111101110011

0001

0010 1001 0100

1010

110101101011

0101

40

Johnson Counter

01001010

10101101

11010110

01101011

10110101

01010010

00001001

10010100

Next StatePresent State

00001000

10001100

11001110

11101111

11110111

01110011

00110001

00010000

TZYXTZYX

41

K-MapsZT

XY 00 01 11 1000 1 101 1 111 1 110 1 1

X(t+1) = T’

ZTXY 00 01 11 10

000111 1 1 1 110 1 0 1 1

Y(t+1) = XY + XZ + XT’

ZTXY 00 01 11 10

0001 1 1 1 111 1 1 1 110

Z(t+1) = Y

ZTXY 00 01 11 10

00 1 101 1 111 1 110 1 1

T(t+1) = Z

42

Unused States in Counters• Remedy

DY = X(Y+Z+T’)

X(t+1) = T’ Y(t+1) = XY + XZ + XT’

Z(t+1) = Y T(t+1) = Z

clock

Z TD Q

C

D Q

C

D Q

C

D Q

C

X Y