16 0 Registers Counters

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  • Registers and Counters

  • OverviewParallel Load RegisterShift Registers

    Serial LoadSerial AdditionShift Register with Parallel LoadBidirectional Shift Register

    *

  • Registers and CountersAn n-bit register = n flip-flops Capable of storing n bits of binary information.A counter is an FSM that goes through a predetermined sequence of states upon the application of clock pulses.

    *

  • 4-Bit Register*

  • Register with parallel load*

  • Shift Register *

  • Serial data transfer*Serial transfer of information from register A to register B

  • Serial addition using shift registersThe two binary numbers to be added serially are stored in two shift registers. The sum bit on the S output of the full adder is transferred into the result register A.

    *

  • Serial vs. parallel additionThe parallel adder is a combinational circuit, whereas the serial adder is a sequential circuit.The parallel adder has n full adders whereas the serial adder requires only one full adder.The serial circuit takes n clock cycles to complete an addition.The serial adder, although it is n times slower, is n times smaller in space.

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  • Shift register with parallel load *

  • Shift register with parallel load *

    ShiftLoadOperation00Nothing01Load parallel1XShift Q0 Q1, Q1Q2

  • Bidirectional shift register *

    S1S0Action00Nothing01Shift down10Shift up11Parallel load

  • Bidirectional Shift Register *

  • CountersA counter is a sequential circuit that goes through a predetermined sequence of states upon the application of clock pulses.Counters are categorized as:

    Synchronous Counter:All FFs receive the common clock pulse, and the change of state is determined from the present state.Ripple Counters: The FF output transition serves as a source for triggering other FFs. No common clock. *

  • Synchronous Binary CountersThe design procedure for a binary counter is the same as any other synchronous sequential circuit.

    Most efficient implementations usually use T-FFs or JK-FFs. We will examine JK and D flip-flop designs.

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  • *J-K Flip Flop Design of a 4-bit Binary Up Counter Synchronous Binary Counters:

  • *J-K Flip Flop Design of a Binary Up Counter (cont.) Synchronous Binary Counters

  • *J-K Flip Flop Design of a Binary Up Counter (cont.) Synchronous Binary Counters

  • *J-K Flip Flop Design of a Binary Up Counter (cont.) Synchronous Binary Counters

  • 20J-K Flip Flop Design of a Binary Up Counter (cont.) Synchronous Binary CountersJQ0 = 1KQ0 = 1

    JQ1 = Q0KQ1 = Q0

    JQ2 = Q0 Q1KQ2 = Q0 Q1

    JQ3 = Q0 Q1 Q2KQ3 = Q0 Q1 Q2

    JKC

    JKC

    JKC

    JKCCLKlogic 1

    Q0

    Q1Q2Q3

  • *J-K Flip Flop Design of a Binary Up Counter with EN and COSynchronous Binary Counters:EN = enable control signal, when 0 counter remains in the same state, when 1 it counts

    CO = carry output signal, used to extend the counter to more stages

    JQ0 = 1 ENKQ0 = 1 ENJQ1 = Q0 ENKQ1 = Q0 ENJQ2 = Q0 Q1 ENKQ2 = Q0 Q1 ENJQ3 = Q0 Q1 Q2 ENKQ3 = Q0 Q1 Q2 ENC0 = Q0 Q1 Q2 Q3 EN

  • PJF*4-bit Upward Synchronous Binary Counter in HDL - Simulation

  • Counter with Parallel LoadAdd path for input data

    enabled for Load = 1Add logic to:

    disable count logic for Load = 1disable feedback from outputsfor Load = 1enable count logic for Load = 0and Count = 1The resulting function table:

    PJF *

    LoadCountAction00Hold Stored Value01Count Up Stored Value1XLoad D

  • Counting Modulo 7: Detect 7 and Asynchronously ClearA synchronous 4-bit binary counterwith an asynchronous Clear isused to make a Modulo7 counter. Use the Clear feature todetect the count 7 andclear the count to 0. Thisgives a count of 0, 1, 2, 3, 4,5, 6, 7(short)0, 1, 2, 3, 4, 5,6, 7(short)0, etc.

    DONT DO THIS! Referred to as a suicide counter! (Count 7 is killed, but the designers job may be dead as well!)

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    Clock

    0

    D3Q3

    D2Q2D1Q1D0Q0CLEARCPLOAD

  • Counting Modulo 7: Synchronously Load on Terminal Count of 6A synchronous 4-bit binarycounter with a synchronousload and an asynchronousclear is used to make a Modulo 7 counter Use the Load feature todetect the count "6" andload in "zero". This givesa count of 0, 1, 2, 3, 4, 5, 6,0, 1, 2, 3, 4, 5, 6, 0, ...

    Using dont cares for statesabove 0110, detection of 6 can be done with Load = Q4 Q2

    *

  • Counting Modulo 6: Synchronously Preset 9 on Reset and Load 9 on Terminal Count 14 A synchronous, 4-bit binarycounter with a synchronousLoad is to be used to make aModulo 6 counter. Use the Load feature topreset the count to 9 onReset and detection ofcount 14.

    This gives a count of 9, 10, 11, 12, 13, 14, 9, 10, 11, 12, 13, 14, 9, If the terminal count is 15 detection is usually built in as Carry Out (CO)

    *

    Clock

    D3Q3

    D2Q2D1Q1D0Q0CLEARCPLOAD

    0011

    Reset

    1

  • Ripple Counter How does it work?

    When there is a positive edge on the clock inputof A, A complementsThe clock input for flip-flop B is the complementedoutput of flip-flop AWhen flip A changesfrom 1 to 0, there is apositive edge on theclock input of Bcausing B tocomplement

    PJF - *

  • Example (cont.) *

  • Ripple Counter (continued)The arrows show thecause-effect relation-ship from the priorslide =>The correspondingsequence of states =>(B,A) = (0,0),

    Each additional bit, C, D, behaves like bit B, changing half as frequently as the bit before it.For 3 bits: (C,B,A) = (0,0,0), (0,0,1), (0,1,0), (0,1,1),(1,0,0), (1,0,1), (1,1,0), (1,1,1), (0,0,0), *

  • Ripple Counter (continued)Starting with C = B = A = 1, equivalent to (C,B,A) = 7 base 10, the next clock increments the count to (C,B,A) = 0 base 10. In fine timing detail:

    The clock to output delaytPHL causes an increasingdelay from clock edge foreach stage transition.Thus, the count ripplesfrom least to mostsignificant bit.For n bits, total worst casedelay is n tPHL. *

  • Example: A 4-bit Upward Counting Ripple Counter *Recall...Less SignificantBit output is Clockfor Next Significant Bit!(Clock is active low)

  • A 4-bit Downward Counting Ripple CounterUse direct Set (S) signals instead of direct Reset (R), in order to start at 1111.Alternative designs:

    Change edge-triggering to positiveConnect the complement output of each FF to the C input of the next FF in the sequence. *

  • P3*Simulation

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