chapter6 counters and registers

8/2/2019 Chapter6 Counters and Registers

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KhoaKhoa KH & KTMTKH & KTMT

BB mnmn KK ThutThut MyMy TnhTnh

2010, CE Department

Bin son ti liu:

Phm Tng Hi

Phan nh Th Duy

Nguyn Trn Hu Nguyn

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2010, CE Department

Ti liu tham kho

Digital Systems, 5th Edition, R.J. Tocci,Prentice Hall, 2001

Digital Logic Desgn Principles, N.

Balabanian & B. Carlson John Wiley &Sons Inc., 2004

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Counters and RegistersCounters and Registers

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Introduction

What is a counter?

Count 1,2,3100 and back to 1,2..

Or represent in state diagram

2 4

68

10

12

4


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Introduction

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Counter using FF

JK FF used to count 3bits numbers startedfrom 000 to 111

Input J=K=1

Clock has negative

going transition Q0Q1Q2 start with 000

and end up with 111

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Asynchronous (Ripple) Counters

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Clock pulses applied only to the FF A

Output from FF A act as an clock input to the FF Band similarly to the others

Output FF DCBA represent 4 bits binary numberwith D as the MSB


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Asynchronous (Ripple) Counters Four-bit asynchronous counter


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Asynchronous (Ripple) Counters


MOD Number

MOD number indicates the number of states in the countingsequence

If 3 FFs were use, the sequence of states would count in

binary from 000 to 111, a total of 8 states. This would becalled a MOD-8 counter.

In general, if N FFs are cascaded, the counter will have 2Ndifferent states, and so it is MOD-2N.

It would be capable of counting up to 2N 1 before returningto its 0 state.

MOD number = 2N

N- the number of FFs


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Example First step involved in building a digital clock is to

take the 60 Hz signal feed into a Schmit-trigger,pulse-shaping circuit to produce a square wave.The 60 Hz square wave is then put into a MOD-60 counter which is used to divide the 60 Hzfrequency by exactly 60 to produce a 1 Hz

waveforms. This 1 Hz waveform is fed to aseries of counters, which then count seconds,minutes, hour, and so on, How many FFs arerequired for the MOD-60 counter?


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Frequency Division

Each FFs divides the frequency of it input by 2. Thus if wewere added a second FF to the chain, the output of thesecond FF would have a frequency equal to of the clockfrequency.

Using the appropriate number of FFs, this circuit could dividea frequency by any power of two.

Using N FFs would produce an output frequency from the last

FF which is equal to 1/2N

of the input frequency.


FF

J

K

Q

Q

CLK

FF

J

K

Q

Q

CLK

1

11

1FF

J

K

Q

Q

CLK

1

1


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Frequency Division Output of each FF basically provides an output

frequency half the frequency of the waveform

To illustrates this, see figure below.


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Frequency Division


The clock signal is 16kHz.

The waveform at output A is an 8-kHz square wave

At output B it is 4 kHz and at output C it is 2 kHz

In any counter, the signal at the output of the last FF

will have a frequency equal to the input clock frequencydivided by the MOD number of the counter

numberMOD

freqCLKinputfrequencysignaloutput =


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Counters with MOD < 2N

The basic asynchronous counter is limited toMOD number = 2N.

This value is the max MOD number that canbe obtained using N FF.

This counter can be modified to produce MOD

numbers less than 2N

by allowing the counterto skip states that are normally part of thecounting sequence.


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How many FF required to design counter with MOD 8

How many FF required to design counter with MOD 7, MOD 6or MOD 5?

Counter circuits

Draw the waveform of each FF CBA


The presence of the NAND

gate will alter the sequence


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1. NAND output is connected to the asynchronous CLR inputof each FF. NAND output is HIGH, no effect on thecounter. When it goes LOW, it will clear all of the FFs sothat the counter immediately goes to the 000 state.

2. Inputs to the NAND gate are the outputs of the B and C

FF, and the NAND output will go LOW whenever B=C=1.This condition will occur when the counter goes from the101 state to 110 state on the NGT of input pulse 6. The

LOW at the NAND output will immediately clear thecounter to the 000 state. Once the FFs have been cleared,the NAND output goes HIGH since the B=C=1 condition nolonger exists.

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Waveform

Start with output A, followed by output B, C and output ofgate NAND

000 001 010 011 100 101 000 - MOD 6

NAND o/p LOW clear

the counter to 000 then

NAND o/p goes back

HIGH


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This counter counts from

000(zero) to 101(five) andthen recycle to 000. It skips110 and 111 so that it goesthrough only six differentstates MOD-6 counter.

Glitch caused by themomentary occurrence of

the 110 state beforeclearing.

000101 001

010

011

100

State Transition Diagram

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General Procedures Counter Design1. Find the smallest number of FF

2. Connect a NAND gate to the Asynchronous CLEAR inputs

of all the FFs

3. Determine which FFs will be in the HIGH state at a count =

X; then connect the normal outputs of these FFs to theNAND gate inputs


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Decade Counters/BCD Counters


MOD-10 counter also referred to as a decadecounter

Decade counter any counter that has 10 distinctstates, no matter what the sequence.

Decade counter which counts in sequence from0000 1001 commonly called a BCD counter,because it uses only the 10 BCD code groups.

Any MOD-10 counter is a decade counter Any decade counter that counts in binary from

0000-1001 is a BCD counter

A decade counter is also often used for dividing apulse frequency exactly by 10.

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Asynchronous Down Counter


All of the counters we have looked were up counters.

Down counter counts number downward e.g: 111 000


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Each FF, except the first must toggle when the precedingFF goes from LOW to HIGH

If the FFs have CLK inputs that respond to negativetransition (HIGH to LOW), then an inverter can be placed infront of each CLK input; however the same effect canaccomplished by driving each FF CLK input from theinverted output of the preceding FF.

Input pulses are applied to A. The A output serves as the

CLK input for B ; the B output serves as the CLK input forthe C.

The waveforms at A, B and C show that B toggles wheneverA goes LOW to HIGH and C toggles whenever B goes LOWto HIGH.

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IC Asynchronous counter


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IC Asynchronous counter



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Example Show how the 74LS293 should be connected

to operate as a MOD-16 counter with a 10-kHzclock input. Determine the frequency at Q3.


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Example

Show how to wire the 74LS293 as a MOD-10counter



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Example Show how to wire a 74LS293 as a MOD-14

counter


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Example

A way to get a MOD-60 counter is shownbelow. Explain how this circuit works.



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Synchronous (Parallel) Counter


The problems encountered with asynchronous arecaused by :

Accumulated FF propagation delays

FFs do not all change states simultaneously in

synchronism with the input pulses.

This limitations can be overcome with the use ofsynchronous or parallel counters

The function is the same to count number, but theoperation is different

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The differences between synchronous andasynchronous:

1. The CLK inputs of all of the FFs are connected together

so that the input signal is applied to each FF

simultaneously

2. Only FF A, the LSB has its J and K inputs permanently

at the HIGH level, The J,K inputs of the others FFs are

driven by some combination of FF outputs

3. The synchronous counter requires more circuitry than

does the asynchronous counter


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Circuit Operation On a given NGT of the clock, only those FFs that are

supposed to toggle on that NGT should have J=K=1 whenthat NGT occurs.

FF A must change states at each NGT. Its J and K inputs arepermanently HIGH so that it will toggle on each NGT of theCLK input.

FF B must change states on each NGT that occurs whileA=1.

FF C must change states on each NGT that occurs whileA=B=1

FF D must change states on each NGT that occurs while

A=B=C=1


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Each FF should have its J&K inputs connected such that they

are HIGH only when the outputs of all lower-order FFs are in

the HIGH state.

Advantages over asynchronous:

1. FFs will change states simultaneously; synchronized to the

NGTs of the input clock pulses.

2. Propagation delays of the FFs do not add together to

produce the overall delay.3. The total response time is the time it takes one FF to

toggle plus the time for the new logic levels to propagatethrough a single AND gate to reach the J, K inputs.

total delay = FF tpd+AND gate tpd

2009

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The control input Up/Downcontrols whether the normal FFoutputs or the inverted FF outputs are fed to the J& K inputsof the successive FFs.

When Up/Down is held HIGH, AND gates 1 and 2 areenabled while AND gate 3 and 4 are disable

This allow the A& B outputs through gates 1 and 2 to the J

and K inputs of FFs B and C. When Up/Down is held LOW , AND gates 1 and 2 are

disabled while AND gates 3 and 4 are enabled.

This allows the A and B outputs through gates 3 and 4 intothe J & K inputs of FFs B and C.


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The first five

clock pulses,

Up/Down = 1,

counter counts

up

The last five

pulses,

Up/Down = 0,

counter counts

down


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Presettable Counters


Presettable can be preset to any desired starting counteither asynchronous or synchronous. Many synchronouscounters that are available in ICs are designed to bepresettable.

This presetting operation is also referred to as parallel

loading the counter.

The J,K & CLK inputs are wired for operation as a parallelup counter.

The asynchronous PRESET & CLEAR inputs are wired toperform asynchronous presetting.

To load the counter with any desired count at any time by:

1. Apply the desired count to the parallel data inputs, P2, P1 & P0.

2. Apply a LOW pulse to the PARALLEL LOAD input, PL

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Presettable Counters Draw the output waveform and understand the

operation of presettable counter



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74LS193/HC193


This is MOD 16 presettable up/down counter withsynchronous counting, asynchronous preset andasynchronous master reset

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74LS193/HC193


Pin Description Clock Inputs CPU and CPD Refer to Mode Select,

if Mode in Count Up CPD must in HIGH state andfor Count Down CPU in HIGH state

Master Reset (MR): Active HIGH and reset thecounter in 0000 state

Preset Inputs: P3 P0 Count Outputs: Q3 Q0 Terminal Count Outputs: are used when two or

more ICs are connected as a multistage to producelarger mode


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(a) Logic on the 74ALS193 for generating TCU ; (b) logic for generating TCD

74LS193/HC193

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Example

Draw the output waveform Q and Terminal Count of the74HC193


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Waveform of 74HC193Waveform of 74HC193

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ExplanationExplanation

At t0 the counter FFs are all low. This causes

TCU to be high

After t1, PL input is pulse LOW. Refer to

MODE table, PL low gives output of counter

loading up the input P3 P0, then the output

Q becomes 1011

At t1, the CPU input makes a PGT, but the

counter cannot response to this because PL

is still active at that time


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Cont.Cont.

At time t2, t3, t4 and t5 the counter counts up

on each PGT at CPU

After t5, the counter is in 1111 state but TCUdoes not go low until CPU goes low at t6

The counter reset to 0000

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ExerciseExercise

Draw the outputwaveform of thefollowing counter


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Decoding a Counter (c thm) Digital counters are used in applications where the count

represented by the states of the FFs must be determined ordisplayed.

Displaying the contents of the counter involves just

connecting the output of each FF to small indicator LED, andthe count can be mentally determined by decoding thebinary states of the LEDs.

But the indicator LED method is inconvenient as the size ofcounter increases.

It would be preferable to develop electronic decoding.

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Active-HIGH Decoding MOD-X counter has X different states.

Decoding network a logic circuit that generates X differentoutputs, each of which detects (decodes) the presence ofone particular state of the counter.

The decoder output can be designed to produce either HIGHor LOW level when detection occurs.

Active-HIGH decoder produces HIGH outputs.

The MOD-8 counter has decoder that consists of eight three-input AND gates

Each AND gate produces a HIGH output for one particularstate of the counter.

Decoding a Counter(c thm)


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Active-LOW Decoding

If NAND gates are used, the decoder outputs will produce anormally HIGH signal, which goes LOW only when thenumber being decoded occurs.

BCD Counter Decoding BCD counter has 10 states. BCD decoders provide 10

outputs corresponding to the decimal digits 0 through 9represented by the states of the counter FFs.

Single display device is used to display the decimal number

0 through 9 One class of decimal displays contains seven small

segments made of material (LED/liquid-crystal display) BCD decoder outputs control which segments are

illuminated in order to produce a pattern representing one ofthe decimal digits.

Decoding a Counter(c thm)

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Cascading BCD Counters(c thm)

Single BCD counter counts from 0 through 9 and thenrecycle to 0. To count to larger decimal values, we can

cascade BCD counter stages.

This multistage arrangements operates as follow:

1. Initially, all counters are cleared to the 0 state. The decimaldisplay is 000.

2. As input pulses arrive,the BCD unit counter advances onecount per pulse. After 9 pulse, the hundred and tens BCDcounters are still at 0, and the units counter is at 9 (binary1001). The decimal display reads 009.

3. On the tenth input pulse the unit counter recycles to 0,causing its FF D output to go from 1 to 0. The decimalreadout is 010.


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4. As additional pulses occur, the units counter advances onecount per pulse, and each time the units counter recyclesto 0, it advances the tens counter one count. After 99 input

pulses have occurred, the tens counter is at 9, as the unitscounter. The decimal readout is 099.

5. On the hundredth input pulse, the units counter recycles to0, which in turn causes the ten counter to recycle to 0. TheFF D output of tens counter makes a 1-to-0 transition,which acts as the clock input for the hundreds counter andcauses it to advance one count. The decimal readout is

100.

6. This process continues up until 999 pulses. On the 1000th

pulse, all of the counters recycle back to 0.

Cascading BCD Counters(c thm)

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Counter asynchronous, synchronous, combinedasynchronous/synchronous

- counting normal binary sequence

000, 001, 010, 011..

Some situations where counter is required follows a

sequence a sequence that is not counting in normal binary.

000, 010, 101,001. In synchronous counters all of the FFs are clocked at the

same time.

The process of designing a synchronous counter, thenbecomes one of designing the logic circuits that decode thevarious states of the counter to supply the logic levels toeach J and K input.

Synchronous Counter Design


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Synchronous Counter DesignDesign procedure

1. Determined thedesired numberof bits (FFs) andthe desiredcounting

sequence.

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2. Draw the statetransition diagramshowing allpossible states,including those

that are not part ofthe desiredcountingsequence.



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3. Use the statetransitiondiagram to setup a table thatlists all

PRESENTstates andtheir NEXTstates.


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4. Add a column to this table for each J & Kinput. For each PRESENT state, indicate thelevels required at each J & K input in order toproduce the transition to the next state.



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5. Design the logic circuits to generate thelevels required at each J & K input.

S dng K_map


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Tnh KA KA = 1


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Tnh JA

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Tnh JB


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Tnh KB

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Tnh Jc


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Tnh KC

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6. Implement the final expressions


chapter6 counters and registers

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