lecture 10 registers, counters and shifters

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ECE C03 Lecture 10 1 Lecture 10 Registers, Counters and Shifters Prith Banerjee ECE C03 Advanced Digital Design Spring 1998

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Lecture 10 Registers, Counters and Shifters. Prith Banerjee ECE C03 Advanced Digital Design Spring 1998. Outline. Registers Register Files Counters Designs of Counters with various FFs Shifters READING: Katz 7.1, 7.2, 7.4, 7.5, 4.7 Dewey 10.2, 10.3, 10.4, Hennessy-Patterson B26. - PowerPoint PPT Presentation

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Page 1: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 1

Lecture 10 Registers, Counters and Shifters

Prith Banerjee

ECE C03

Advanced Digital Design

Spring 1998

Page 2: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 2

Outline

• Registers• Register Files• Counters • Designs of Counters with various FFs• Shifters• READING: Katz 7.1, 7.2, 7.4, 7.5, 4.7 Dewey

10.2, 10.3, 10.4, Hennessy-Patterson B26

Page 3: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 3

Building Complex Memory Elements

• Flipflops: most primitive "packaged" sequential circuits

• More complex sequential building blocks:

Storage registers, Shift registers, Counters Available as components in the TTL Catalog

• How to represent and design simple sequential circuits: counters

• Problems and pitfalls when working with counters:

Start-up States Asynchronous vs. Synchronous logic

Page 4: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 4

Registers

• Storage unit. Can hold an n-bit value• Composed of a group of n flip-flops

– Each flip-flop stores 1 bit of information

• Normally use D flip-flopsD Q

Dffclk

D QDffclk

D QDffclk

D QDffclk

Page 5: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 5

Controlled RegisterReset Load Action0 0 Q = old Q1 0 Q = 00 1 Q = D

D QDffclk

D QDffclk

D QDffclk

D QDffclk

Page 6: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 6

RegistersGroup of storage elements read/written as a unit

4-bit register constructed from 4 D FFsShared clock and clear lines

TTL 74171 Quad D-type FF with Clear(Small numbers represent pin #s on package)

Schematic Shape

Q1

CLR

D3D2D1D0

171

Q1

Q0Q0

CLK Q3Q3Q2Q2

11

109

5

67

43

2

14

13

151

12

Page 7: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 7

Variations of RegistersSelective Load CapabilityTri-state or Open Collector OutputsTrue and Complementary Outputs

74377 Octal D-type FFswith input enable

74374 Octal D-type FFswith output enable

EN enabled low andlo-to-hi clock transition

to load new data intoregister

OE asserted lowpresents FF state to

output pins; otherwisehigh impedence

D3

D6Q5

Q2

377

Q1Q0

Q3

EN CLK

Q6

Q4

Q7

D5

D2D1D0

D4

D7

1

3478

13141718

11

256912151619

HGFEDCBA

QHQGQFQEQDQCQBQA

OE

37411

1

3478

13141718

256912151619

CLK

Page 8: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 8

Register FilesTwo dimensional array of flipflopsAddress used as index to a particular wordWord contents read or written

74670 4x4 Register File withTri-state Outputs

Separate Read and Write EnablesSeparate Read and Write AddressData Input, Q Outputs

Contains 16 D-ffs, organized asfour rows (words) of four elements (bits)

670

Q4

D1

D4D3D2

Q3Q2Q1

WE

WAWB

RE

RARB

54

11

1413

12

15123

10976

Page 9: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 9

Shift RegistersStorage + ability to circulate data among storage elements

Shift from left storage element to right neighbor on every lo-to-hi transition on shift signal

Wrap around from rightmost element to leftmost element

Master Slave FFs: sample inputs while clock is high; change outputs on falling edge

Shift Direction\Reset

\ResetShift

Q 1 1 0 0 0

Q 2 0 1 0 0

Q 3 0 0 1 0

Q 4 0 0 0 1

Shift

Shift

Shift

JK

JK

JK

JK

QQ

QQ

QQ

QQ

Shift

Q1

Q2

Q3

Q4

Page 10: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 10

Shift Registers I/OSerial vs. Parallel InputsSerial vs. Parallel OutputsShift Direction: Left vs. Right

74194 4-bit UniversalShift Register

Serial Inputs: LSI, RSIParallel Inputs: D, C, B, AParallel Outputs: QD, QC, QB, QAClear SignalPositive Edge Triggered Devices

S1,S0 determine the shift functionS1 = 1, S0 = 1: Load on rising clk edge synchronous loadS1 = 1, S0 = 0: shift left on rising clk edge LSI replaces element DS1 = 0, S0 = 1: shift right on rising clk edge RSI replaces element AS1 = 0, S0 = 0: hold state

Multiplexing logic on input to each FF!

Shifters well suited for serial-to-parallel conversions, such as terminal to computer communications

QDQCQBQA

Page 11: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 11

Application of Shift RegistersParallel to Serial Conversion

QAQBQCQD

S1S0LSIDCBA

RSICLK

CLR

QAQBQCQD

S1S0LSIDCBA

RSICLK

CLR

D7D6D5D4

Sender

D3D2D1D0

QAQBQCQD

S1S0LSIDCBA

RSICLK

CLR

QAQBQCQD

S1S0LSIDCBA

RSICLK

CLR

Receiver

D7D6D5D4

D3D2D1D0

Clock

194 194

194194

ParallelInputs

Serialtransmission

ParallelOutputs

Page 12: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 12

Counters

Proceed through a well-defined sequence of states in response to count signal

3 Bit Up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000, ...

3 Bit Down-counter: 111, 110, 101, 100, 011, 010, 001, 000, 111, ...

Binary vs. BCD vs. Gray Code Counters

A counter is a "degenerate" finite state machine/sequential circuitwhere the state is the only output

A counter is a "degenerate" finite state machine/sequential circuitwhere the state is the only output

Page 13: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 13

Johnson Counters

End-Around

8 possible states, single bit change per state, useful for avoiding glitches

J CLK K

S

R

Q

Q

+

+

+ +

0 1

Shift

Q 1 Q 2 Q 3 Q 4

\Reset

J

K

S

R

Q

Q

J

K

S

R

Q

Q

J

K

S

R

Q

Q CLK CLK CLK

1

0

0

0

1

1

0

0

1

1

1

0

1

1

1

1

0

1

1

1

0

0

1

1

0

0

0

1

0

0

0

0

Shift

Q 1

Q 2

Q 3

Q 4

100

Page 14: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 14

Catalog Counters

74163 Synchronous4-Bit Upcounter

Synchronous Load and Clear Inputs

Positive Edge Triggered FFs

Parallel Load Data from D, C, B, A

P, T Enable Inputs: both must be asserted to enable counting

RCO: asserted when counter enters its highest state 1111, used for cascading counters "Ripple Carry Output"

74161: similar in function, asynchronous load and reset

QAQBQCQD

163RCO

PT

ABCD

LOAD

CLR

CLK2

710

15

9

1

3456

14

1211

13

Page 15: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 15

74163 Detailed Timing Diagram

CLK

A

B

C

D

LOAD

CLR

P

T

Q A

Q B

Q C

Q D

RCO 12 13 14 15 0 1 2

Clear Load Count Inhibit

Page 16: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 16

Counter Design ProcedureThis procedure can be generalized to implement ANY finite state machine

Counters are a very simple way to start: no decisions on what state to advance to next current state is the output

Example: 3-bit Binary Upcounter

000

001

State TransitionTable

FlipflopInput Table

Decide to implement withToggle Flipflops

What inputs must bepresented to the T FFsto get them to change

to the desired state bit?

This is called"Remapping the Next

State Function"

PresentState

NextState

FlipflopInputs

C B A C+ B+ A+ TC TB TA

0 0 0 0 0 1 0 0 10 0 1 0 1 0 0 1 10 1 0 0 1 1 0 0 10 1 1 1 0 0 1 1 11 0 0 1 0 1 0 0 11 0 1 1 1 0 0 1 11 1 0 1 1 1 0 0 11 1 1 0 0 0 1 1 1

Page 17: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 17

Example Design of CounterK-maps for Toggle

Inputs:Resulting Logic Circuit:

CB00 01 11 10A

0

1

TA =

CB00 01 11 10A

0

1

TB =

CB00 01 11 10A

0

1

TC =

Page 18: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 18

Count

\Reset

Q C

Q B

Q A

100

Resultant Circuit for CounterK-maps for Toggle

Inputs:Resulting Logic Circuit:

Timing Diagram:

T

CLK

\Reset

Q

Q

S

R

QAT

CLK

Q

Q

S

R

QBT

CLK

Q

Q

S

R

QC

Count

+

TB = A

TC = A • B

T A = 1

CB A

C

00 01 11 10

0

1

B

1 1 1 1

1 1 1 1

CB

A

C

00 01 11 10

0

1

B

0 0 0 0

1 1 1 1

CB A

C

B

00 01 11 10

0

1

0 0 0 0

0 1 1 0

Page 19: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 19

More Complex Counter Design

Step 1: Derive the State Transition Diagram

Count sequence: 000, 010, 011, 101, 110

Step 2: State Transition Table

PresentState

NextState

0 0 0 0 1 00 1 0 0 1 10 1 1 1 0 11 0 1 1 1 01 1 0 0 0 0

Page 20: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 20

Complex Counter Design (Contd)

Step 1: Derive the State Transition Diagram

Count sequence: 000, 010, 011, 101, 110

Step 2: State Transition Table

Note the Don't Care conditions

PresentState

NextState

0 0 0 0 1 00 0 1 X X X0 1 0 0 1 10 1 1 1 0 11 0 0 X X X1 0 1 1 1 01 1 0 0 0 01 1 1 X X X

Page 21: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 21

Counter Design (Contd)Step 3: K-Maps for Next State Functions

CB00 01 11 10A

0

1

C+ =

CB00 01 11 10A

0

1

A+ =

CB00 01 11 10A

0

1

B+ =

Page 22: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 22

Counter Design (contd)Step 4: Choose Flipflop Type for Implementation Use Excitation Table to Remap Next State Functions

Toggle ExcitationTable

Remapped Next StateFunctions

PresentState

ToggleInputs

Q Q+ T

0 0 00 1 11 0 11 1 0

0 0 0 0 1 00 0 1 X X X0 1 0 0 0 10 1 1 1 1 01 0 0 X X X1 0 1 0 1 11 1 0 1 1 01 1 1 X X X

C B A TC TB TA

Page 23: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 23

Resultant Counter DesignRemapped K-Maps

CB00 01 11 10A

0

1

TC

CB00 01 11 10A

0

1

TA

CB00 01 11 10A

0

1

TB

TC = A C + A C = A xor C

TB = A + B + C

TA = A B C + B C

Page 24: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 24

Resultant Circuit for Complex Counter

Resulting Logic:

Timing Waveform:

5 Gates13 Input Literals + Flipflop connections

TCT

CLK

Q

Q

S

RCount

T

CLK

Q

Q

S

R

TBC

\C

B A

\B \A

TAT

CLK

Q

Q

S

R

\Reset

0

0

0

0

0

0

0

1

0

0

1

1

1

0

1

1

1

0

0

0

0

100

Count

\Reset

C

B

A

TC

TBTA

AC

A\BC

\ABC\BC

Page 25: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 25

Implementing Counters with Different FFs

• Different counters can be implemented best with different counters

• Steps in building a counter– Build state diagram

– Build state transition table

– Build next state K-map

• Implementing the next state function with different FFs• Toggle flip flops best for binary counters• Existing CAD software for finite state machines favor D

FFs

Page 26: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 26

Implementing 5-state counter with RS FFs

Continuing with the 000, 010, 011, 101, 110, 000, ... counter example

RS Exitation Table

Remapped Next State Functions

Q+ = S + R Q

PresentState

NextState

0 0 0 0 1 0 X 0 0 1 X 0 0 0 1 X X X X X X X X X0 1 0 0 1 1 X 0 0 X 0 10 1 1 1 0 1 0 1 1 0 0 X1 0 0 X X X X X X X X X1 0 1 1 1 0 0 X 0 1 1 01 1 0 0 0 0 1 0 1 0 X 01 1 1 X X X X X X X X X

Q Q+ R S

0 0 X 00 1 0 11 0 1 01 1 0 X

Rmepped next state

RC SC RB SB RA SA

Page 27: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 27

Implementation with RS FFsRS FFs Continued

RC = A

SC = A

RB = A B + B C

SB = B

RA = C

SA = B C

CB00 01 11 10A

0

1

RC

CB00 01 11 10A

0

1

RA

CB00 01 11 10A

0

1

RB

CB00 01 11 10A

0

1

SC

CB00 01 11 10A

0

1

SA

CB00 01 11 10A

0

1

SB

X X 1 X

X 0 X 0

0 0 0 X X 1 X X

0 0 1 X

X 1 X 0

1 X 0 X

X 0 X 1

X 0 X XX 0 X 1

0 1 0 XX X X 0

Page 28: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 28

Implementation With RS FFs

Resulting Logic Level Implementation: 3 Gates, 11 Input Literals + Flipflop connections

CLK CLK CLK

\ A R

S A

C

\ C

Q

Q

RB

\ B

R

S

Q

Q \ B

B C

SA

R

S

A

\A

B

A C B

\C RB SA

Q

Q

Count

Page 29: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 29

Implementing with JK FFs

Continuing with the 000, 010, 011, 101, 110, 000, ... counter example

RS Exitation Table

Remapped Next State Functions

Q+ = S + R Q

PresentState

NextStateQ Q+ J K

0 0 0 X0 1 1 X1 0 X 11 1 X 0

Rmepped next stateJC KC JB KB JA KA

0 0 0 0 1 0 0 X 1 X 0 X 0 0 1 X X X X X X X X X0 1 0 0 1 1 0 X X 0 1 X0 1 1 1 0 1 1 X X 1 X 01 0 0 X X X X X X X X X1 0 1 1 1 0 X 0 1 X X 11 1 0 0 0 0 X 1 X 1 0 X1 1 1 X X X X X X X X X

Page 30: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 30

Implementation with JK FFsCB

00 01 11 10A

0

1

JC

CB00 01 11 10A

0

1

JA

CB00 01 11 10A

0

1

JB

CB00 01 11 10A

0

1

KC

CB00 01 11 10A

0

1

KA

CB00 01 11 10A

0

1

KB

JC = A

KC = A/

JB = 1

KB = A + C

JA = B C/

KA = C

Page 31: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 31

Implementation with JK FFs

Resulting Logic Level Implementation: 2 Gates, 10 Input Literals + Flipflop Connections

CLK CLK CLK J

K

Q

Q

A

\ A

C

\ C KB

J

K

Q

Q

B

\ B

+

J

K

Q

Q

JA

C

A

\ A

B \ C

Count

A C KB JA

Page 32: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 32

Implementation with D FFsSimplest Design Procedure: No remapping needed!

DC = A

DB = A C + B

DA = B C

Resulting Logic Level Implementation: 3 Gates, 8 Input Literals + Flipflop connections

CLK CLK

D Q

Q

A

\ A

D Q

Q

DA DB B

\ B CLK

D Q

Q

A C

\ C Count

\ C \ A

\ B

B \ C DA DB

Page 33: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 33

Comparison with Different FF Types• T FFs well suited for straightforward binary counters

But yielded worst gate and literal count for this example!

• No reason to choose R-S over J-K FFs: it is a proper subset of J-K

R-S FFs don't really exist anyway

J-K FFs yielded lowest gate count

Tend to yield best choice for packaged logic where gate count is key

• D FFs yield simplest design procedure

Best literal count

D storage devices very transistor efficient in VLSI

Best choice where area/literal count is the key

Page 34: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 34

Asynchronous vs. Synchronous Counters

Ripple Counters

Deceptively attractive alternative to synchronous design style

Count signal ripples from left to right

State transitions are not sharp!

Can lead to "spiked outputs" from combinational logic decoding the counter's state

Can lead to "spiked outputs" from combinational logic decoding the counter's state

T

Count

Q

QA

T Q

QB

T

CLK

Q

QC

CLK CLK

CountResetA

B

C

Page 35: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 35

Clock

Load

D

C

B

A

100

Power of Synchronous Clear and Load

Starting Offset Counters: e.g., 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1111, 0110, ...

Use RCO signal to trigger Load of a new state

Since 74163 Load is synchronous, state changes only on the next rising clock edge

0110is the state

to be loaded

D C B A

L O A D

C L R

C L K

R C O

P T

Q A

Q B

Q C

Q D1

6 3

Load

D C B A

0 1++

Page 36: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 36

Shifters

• We have discussed some core logic design circuits for designing datapaths of computers– adders

– ALUs

– multipliers

• A final component which is very important is a shifter– Takes a n-bit input and performs a shift left or right by m bits

– Can define arithmetic shifts, logical shifts or circular shifts, e.g. circular shift left

a7 a6 a5 a4 a3 a2 a1 a0

a6 a5 a4 a3 a2 a1 a0 a7

Page 37: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 37

8-input Barrel Shifter

Specification:

Inputs: D7, D6, …, D0Outputs: O7, O6, …, O0Control: S2, S1, S0

shift input the specified numberof positions to the right

D7D6D5D4D3D2D1D0

O7O6O5O4O3O2O1O0

.

.

.

S2, S1, S0 = 0 0 0

D7D6D5D4D3D2D1D0

O7O6O5O4O3O2O1O0

.

.

.

S2, S1, S0 = 0 0 1

D7D6D5D4D3D2D1D0

O7O6O5O4O3O2O1O0

.

.

.

S2, S1, S0 = 0 1 0

Understand the problem:

Page 38: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 38

Functional Description of Shifter

Boolean equations

O7 = S2' S1' S0' D7 + S2' S1' S0 D6 + … + S2 S1 S0 D0

O6 = S2' S1' S0' D6 + S2' S1' S0 D5 + … + S2 S1 S0 D7

O5 = S2' S1' S0' D5 + S2' S1' S0 D4 + … + S2 S1 S0 D6

O4 = S2' S1' S0' D4 + S2' S1' S0 D3 + … + S2 S1 S0 D5

O3 = S2' S1' S0' D3 + S2' S1' S0 D2 + … + S2 S1 S0 D4

O2 = S2' S1' S0' D2 + S2' S1' S0 D1 + … + S2 S1 S0 D3

O1 = S2' S1' S0' D1 + S2' S1' S0 D0 + … + S2 S1 S0 D2

O0 = S2' S1' S0' D0 + S2' S1' S0 D7 + … + S2 S1 S0 D1

O7 D7 D6 D5 D4 D3 D2 D1 D0

O6 D6 D5 D4 D3 D2 D1 D0 D7

O5 D5 D4 D3 D2 D1 D0 D7 D6

O4 D4 D3 D2 D1 D0 D7 D6 D5

O3 D3 D2 D1 D0 D7 D6 D5 D4

O2 D2 D1 D0 D7 D6 D5 D4 D3

O1 D1 D0 D7 D6 D5 D4 D3 D2

O0 D0 D7 D6 D5 D4 D3 D2 D1

S2 0 0 0 0 1 1 1 1

S1 0 0 1 1 0 0 1 1

S0 0 1 0 1 0 1 0 1

Function Table

Page 39: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 39

8-input Barrel Shifter

• Straightforward gate level implementation– Looking at the Boolean equations earlier it is not

possible to simplify them

• Discrete gate implementation would require– eight 4-input AND gates and one 8-input OR gate per

outputfunction

– total 64 8-input AND gates, and 8 8-input OR gates for 8 output functions

– Requires 40 TTL SSI packages

Page 40: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 40

Alternative Implementations of Shifter

• Use MSI components such as multiplexers and decoders

• Each output function can be implemented by an 8:1 multiplexer, need eight MUXex, eight packages

• Use the control input S2 S1 S0 to control mux

S2S1S0

D7D6…D1D0

O7

S2S1S0

D7D6…D1D0

S2S1S0

D7D6…D1D0

O0O6

Page 41: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 41

Shifter Design Using Switching Logic

O7 O6 O5 O4 O3 O2 O1 O0

D7

D6

D5

D4

D3

D2

D1

D0

S000

S001S001

O7 O6 O5 O4 O3 O2 O1 O0

D7

D6

D5

D4

D3

D2

D1

D0

S000

S001 S001

S010 S010

S011

S100

S101

S110

S111

S011

S100

S101

S110

S111

Crosspoint switches Fully Wired crosspoint switch

•Remember that one can use CMOS transistors as switchesthat turn on when the gate signal is high, and off when gate signal is low•Need 64 switches (transistors) plus a decoder in a regular design

Page 42: Lecture 10  Registers, Counters and Shifters

ECE C03 Lecture 10 42

Summary

• Registers• Register Files• Counters• Designs of Counters with various FFs• Shifters• NEXT LECTURE: Memory Design• READING: Katz 7.6