11/15/2004 EE 42 fall 2004 lecture 32 1

Lecture #32 Registers, counters etc.

• Last lecture: – Digital circuits with feedback– Clocks– Flip-Flops

• This Lecture:– Edge triggers– Registers– shift registers– counters

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Edge triggering

• The last lecture ended with how a flip flop could be designed by using two latches which cascaded in a master-slave relationship.

• Another way of creating an edge triggered flip flop is to use logic with feedback, as in the following slide.

11/15/2004 EE 42 fall 2004 lecture 32 3

Q

D

Clk=1

R

SQ’

negative edge-triggered D flip-flop (D-FF)

4-5 gate delays

must respect setup and hold time constraints to successfully

capture input

characteristic equationQ(t+1) = D

holds D' whenclock goes low

holds D whenclock goes low

Edge-Triggered Flip-Flops

• More efficient solution: only 6 gates– sensitive to inputs only near edge of clock signal (not while high)

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positive edge-triggered FF

negative edge-triggered FF

D

CLKQpos

Qpos'

Qneg

Qneg'

100

Edge-Triggered Flip-Flops (cont’d)

• Positive edge-triggered– Inputs sampled on rising edge; outputs change after rising edge

• Negative edge-triggered flip-flops– Inputs sampled on falling edge; outputs change after falling edge

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Timing Methodologies

• As we have seen, there are several different ways of designing a sequential logic circuit. In general, each circuit will stick with a set of rules which are designed to achieve consistently accurate results.

• A set of rules for interconnecting components and clocks are adopted which will guarantee proper operation of system when strictly followed.

• Approach depends on building blocks used for memory elements. Edge-triggered flip-flops are found in programmable logic devices

• Many custom integrated circuits focus on level-sensitive latches

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• Basic rules for correct timing:– Inputs to flip-flops are stable and correct for

and interval around the time of sampling (avoid asynchronous inputs wherever possible)

– No flip-flop changes state more than once per clocking event

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clock

datachangingstable

input

clock

Tsu Th

clock

dataD Q D Q

Definition: Set up time/hold time

To ensure that the data signal is captured accurately, the data must be stable for an time tsu (set up) before the edge, and kept constant for a time th (hold) after the edge.

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behavior is the same unless input changeswhile the clock is high

D Q

CLK

positiveedge-triggered

flip-flop

D QG

CLK

transparent(level-sensitive)

latch

D

CLK

Qedge

Qlatch

Comparison of Latches and Flip-Flops

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Type When inputs are sampled When output is valid

unclocked always propagation delay from input changelatch

level-sensitive clock high propagation delay from input changelatch (Tsu/Th around falling or clock edge (whichever is later)

edge of clock)

master-slave clock high propagation delay from falling edgeflip-flop (Tsu/Th around falling of clock

edge of clock)

negative clock hi-to-lo transition propagation delay from falling edgeedge-triggered (Tsu/Th around falling of clockflip-flop edge of clock)

Comparison of Latches and Flip-Flops (cont’d)

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all measurements are made from the clocking event that is, the rising edge of the clock

Typical Timing Specifications

• Positive edge-triggered D flip-flop– Setup and hold times– Minimum clock width– Propagation delays

Th

0.5 ns

Tw 1ns

Tsu

0.8 nsD

CLK

Tsu

0.8 nsTh

0.5 ns

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IN

Q0

Q1

CLK

100

Cascading Edge-triggered Flip-Flops

• Shift register– New value goes into first stage– While previous value of first stage goes into second stage– The propagation time must be longer than the hold time

CLK

INQ0 Q1

D Q D Q OUT

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timing constraintsguarantee proper

operation ofcascaded components

assumes infinitely fast distribution of the clock

Cascading Edge-triggered Flip-Flops (cont’d)

• Why this works– Propagation delays exceed hold times– Clock width constraint exceeds setup time– This guarantees following stage will latch current value before it

changes to new value

Tsu

4ns

Tp

3ns

Th

2ns

In

Q0

Q1

CLK

Tsu

4ns

Tp

3ns

Th

2ns

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original state: IN = 0, Q0 = 1, Q1 = 1due to skew, next state becomes: Q0 = 0, Q1 = 0, and not Q0 = 0, Q1 = 1

CLK1 is a delayedversion of CLK0

In

Q0

Q1

CLK0

CLK1

100

Clock Skew• The problem

– Correct behavior assumes next state of all storage elementsdetermined by all storage elements at the same time

– This is difficult in high-performance systems because time for clock to arrive at flip-flop is comparable to delays through logic

– Effect of skew on cascaded flip-flops:

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Summary of Latches and Flip-Flops

• Development of D-Flip-Flop– Level-sensitive used in custom integrated circuits

• can be made with 4 gates

– Edge-triggered used in programmable logic devices

– Good choice for data storage register

• Historically J-K Flip Flop was popular but now never used– Similar to R-S but with 1-1 being used to toggle output (complement state)

– Can always be implemented using D-FF

• Preset and clear inputs are highly desirable on flip-flops– Used at start-up or to reset system to a known state

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Flip-Flop Features• Reset (set state to 0) – R

– Synchronous: Dnew = R' • Dold (when next clock edge arrives)

– Asynchronous: doesn't wait for clock, quick but dangerous

• Preset or set (set state to 1) – S (or sometimes P)– Synchronous: Dnew = Dold + S (when next clock edge arrives)

– Asynchronous: doesn't wait for clock, quick but dangerous

• Both reset and preset– Dnew = R' • Dold + S (set-dominant)

– Dnew = R' • Dold + R'S (reset-dominant)

• Selective input capability (input enable/load) – LD or EN– Multiplexer at input: Dnew = LD' • Q + LD • Dold

– Load may/may not override reset/set (usually R/S have priority)

• Complementary outputs – Q and Q'

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R S R S R S

D Q D Q D Q D Q

OUT1 OUT2 OUT3 OUT4

CLK

IN1 IN2 IN3 IN4

R S

"0"

Registers

• Collections of flip-flops with similar controls and logic– Stored values somehow related (e.g., form binary value)– Share clock, reset, and set lines– Similar logic at each stage

• Examples– Shift registers– Counters

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D Q D Q D Q D QIN

OUT1 OUT2 OUT3 OUT4

CLK

Shift Register

• Holds samples of input– Store last 4 input values in sequence– 4-bit shift register:

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parallel inputs

parallel outputs

serial transmission

Shift Register Application

• Parallel-to-serial conversion for serial transmission

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D Q D Q D Q D QIN

OUT1 OUT2 OUT3 OUT4

CLK

OUT

Pattern Recognizer

• Combinational function of input samples– In this case, recognizing the pattern 1001 on

the single input signal

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D Q D Q D Q D Q

OUT1 OUT2 OUT3 OUT4

CLK

"1"

Binary Counter

• Logic between registers (not just multiplexer)– XOR decides when bit should be toggled– Always for low-order bit, only when first bit is true for

second bit, and so on

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Sequential Logic Summary

• Fundamental building block of circuits with state– R-S latch, R-S master/slave, D master/slave, edge-triggered D FF

– Latch and flip-flop

• Timing methodologies– Use of clocks

– Cascaded FFs work because prop delays exceed hold times

– Beware of clock skew

• Asynchronous inputs and their dangers– Synchronizer failure: what it is and how to minimize its impact

• Basic registers– Shift registers

– Pattern detectors

– Counters