1 EE365 Sequential PLD timing Registers Counters Shift registers

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  • Slide 1
  • 1 EE365 Sequential PLD timing Registers Counters Shift registers
  • Slide 2
  • 2 Sequential PLD timing parameters
  • Slide 3
  • 3 Timing contd.
  • Slide 4
  • 4 Multibit registers and latches 74x175
  • Slide 5
  • 5 8-bit (octal) register 74x374 3-state output
  • Slide 6
  • 6 Other octal registers 74x273 asynchronous clear Non-three state output 74x377 clock enable no tristate-buffer
  • Slide 7
  • 7 Octal latch 74x373 Output enable Latch-enable input C or G Register vs. latch, whats the difference? Register: edge-triggered behavior Latch: output follows input when G is asserted
  • Slide 8
  • 8 Counters Any sequential circuit whose state diagram is a single cycle. RESET EN
  • Slide 9
  • 9
  • Slide 10
  • 10 LSB MSB Synchronous counter Serial enable logic
  • Slide 11
  • 11 LSB MSB Synchronous counter Parallel enable logic
  • Slide 12
  • 12 74x163 MSI 4-bit counter
  • Slide 13
  • 13 74x163 internal logic diagram XOR gates embody the T function Mux-like structure for loading
  • Slide 14
  • 14 Counter operation Free-running 16 Count if ENP and ENT both asserted. Load if LD is asserted (overrides counting). Clear if CLR is asserted (overrides loading and counting). All operations take place on rising CLK edge. RCO is asserted if ENT is asserted and Count = 15.
  • Slide 15
  • 15 Free-running 4-bit 163 counter divide-by-16 counter
  • Slide 16
  • 16 Modified counting sequence Load 0101 (5) after Count = 15 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 5, 6, divide-by-11 counter
  • Slide 17
  • 17 Another way Clear after Count = 1010 (10) 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2, 3, modulo-11 or divide-by-11 counter trick to save gate inputs
  • Slide 18
  • 18 Counting from 3 to 12
  • Slide 19
  • 19 Cascading counters RCO (ripple carry out) is asserted in state 15, if ENT is asserted.
  • Slide 20
  • 20 Decoding binary-counter states
  • Slide 21
  • 21 Decoder waveforms Glitches may or may not be a concern.
  • Slide 22
  • 22 Glitch-free outputs Registered outputs delayed by one clock tick. Well show another way to get the same outputs later, using a shift register.
  • Slide 23
  • 23 Shift registers For handling serial data, such as RS- 232 and modem transmission and reception, Ethernet links, etc. Serial-in, serial-out
  • Slide 24
  • 24 Serial-to-parallel conversion Use a serial-in, parallel-out shift register
  • Slide 25
  • 25 Parallel-to-serial conversion Use parallel-in, serial-out shift register mux
  • Slide 26
  • 26 Do both Parallel-in, parallel-out shift register
  • Slide 27
  • 27 Universal shift register 74x194 Shift left Shift right Load Hold
  • Slide 28
  • 28 One stage of 194
  • Slide 29
  • 29 Shift-register counters Ring counter
  • Slide 30
  • 30 Johnson counter Twisted ring counter
  • Slide 31
  • 31 LFSR counters Pseudo-random number generator 2 n - 1 states before repeating Same circuits used in CRC error checking in Ethernet networks, etc.