chapter 9 counters and shift registers. 2 counter: a sequential circuit that counts pulses. used for...

Chapter 9

Counters and Shift Registers

2

Counters and Shift Registers

• Counter: A Sequential Circuit that counts pulses. Used for Event Counting, Frequency Division, Timing, and Control Operations.

• Shift Register: A Sequential Circuit that moves stored data bits in a specific direction. Used in Serial Data Transfers, SIPO/PISO Conversions, Arithmetic, and Delays.

3

Counter Terminology – 1

• A Counter is a digital circuit whose outputs progress in a predictable repeating pattern. It advances on state for each clock pulse.

• State Diagram: A graphical diagram showing the progression of states in a sequential circuit such as a counter.

4

Counter Terminology – 2

• Count Sequence: The specific series of output states through which a counter progresses.

• Modulus: The number of states a counter sequences through before repeating (mod-n).

• Counter directions:– UP - count high to low (MSB to LSB)– DOWN - count low to high (LSB to MSB).

5

Counter Modulus

• Modulus of a counter is the number of states through which a counter progresses.

• A Mod-12 UP Counter counts 12 states from 0000 (010) to 1011 (1110). The process then repeats.

• A Mod-12 DOWN counter counts from 1011 (1110) to 0000 (010), then repeats.

6

State Diagram

• A diagram that shows the progressive states of a sequential circuit.

• The progression from one state to the next state is shown by an arrow. – (0000 0001 0010).

• Each state progression is caused by a pulse on the clock to the sequential circuit.

7

MOD 12 Counter State Diagram

• With each clock pulse the counter progresses by one state from its present position on the state diagram to the next state in the sequence.

• This close system of counting and adding is known as modulo arithmetic.

8

MOD 12 Counter State Diagram

9

Truncated Counters – 1

• An n-bit counter that counts the maximum modulus (2n) is called a full-sequence counter such as Mod 2, Mod 4, Mod 8, etc.

• An n-bit counter whose modulus is less than the maximum possible is called a truncated sequence counter, such as mod 3 (n = 2), mod 12 (n = 4).

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• A 4-bit mod 12 UP counter that counts from 0000 to 1011 is an example of a truncated counter.

• A 4-bit mod 16 UP counter that counts up from 0000 to 1111 is an example of a full-sequence counter.

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12

Counter Timing Diagrams – 1

• Shows the timing relationships between the input clock and the outputs Q3, Q2, Q1, …Qn of a counter.

• For a 4-bit mod 16 counter, the output Q0 changes for every clock pulse, Q1 changes on every two clock pulses, Q2 on four, and Q3 on 8 clocks.

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• The outputs (Q0 Q3) of the counter can be used as frequency dividers with Q0 = clock 2, Q1 = clock 4, Q2 = clock 8, and Q3 = clock 16.

• The frequency is based on T of the output, not a transition on the output.

• The same is true for a mod 12, except Q3 = clock 12.

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Synchronous Counters

• A counter whose flip-flops are all clocked by the same source and change state in synchronization.

• The memory section keeps track of the present state.

• The control section directs the counter to the next state using command and status lines.

17

Synchronous Counters

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Analysis of Synchronous Counters – 1

• Set equations for the (JK, D, T) inputs in terms of the Q outputs for the counter.

• Set up a table similar to the one in Table 9.5 and place the first initial state in the present state column (usually all 000).

• Use the initial state to fill in the Inputs that will cause this state on a clock pulse.

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• Determine the result on each FF in the counter and place this in the next state.

• Enter the next state on the present state line 2 and repeat the process until you cycle back to the first initial state.

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State Table For Figure 9.11Present State Next State

000 01 ( R ) 00 (NC) 11 ( T ) 001

001 01 ( R ) 11 (T) 11 ( T ) 010

010 01 ( R ) 00 (NC) 11 ( T ) 011

011 11 ( T ) 11 (T) 11 ( T ) 100

100 01 ( R ) 00 (NC) 01 ( R ) 000

Synchronous Inputs

012 QQQ 012 QQQ22KJ 11KJ 00KJ

22

Basic Design Approach – 1

• Draw a state diagram showing state changes and inputs and outputs.

• Create a present/next state table.

• List present states in binary order and next states based on the state diagram.

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• Use FF Excitation Tables to determine FF (JK, D, T) inputs for each present next state transition.

• Specify inputs equations for each input and simplify using Boolean reductions.

• A VHDL design for counters is done more easily and is not as time consuming.

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• The previous two slides describe the process for designing counters by deriving and simplifying Boolean equations for a counter (classical approach).

• VHDL design for counters is done more easily and is not as time consuming.

25

VHDL Process Statements

• Sequential counters use a process statement to control transitions to the next count state.

• A VHDL Attribute is used with an identifier (signal) to define clock edges.

• Clock uses an attribute called EVENT such as (clk’EVENT AND clk=‘1) to define a rising edge clock event.

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VHDL UP Counter

-- simple_int_counter.vhd

-- 8-bit synchronous counter with asynchronous clear.

-- Uses INTEGER type for counter output.

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

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VHDL UP Counter Entity

ENTITY simple_int_counter IS

PORT(

clock : IN STD_LOGIC;

reset : IN_STD_LOGIC;

q : OUT INTEGER RANGE 0 TO 255);

END simple_int_counter;

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VHDL UP Counter Architecture – 1

ARCHITECTURE counter OF simple_int_counter IS

BEGIN

PROCESS (clock, reset)

VARIABLE count : INTEGER RANGE 0 to 255;

BEGIN

IF (reset = ‘0’) THEN

COUNT : = 0;

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VHDL UP Counter Architecture – 2 ELSE

IF (clock’ EVENT AND clock = ‘1’) THEN

count := count +1;

END IF;

END IF;

q <= count;

END PROCESS;

END counter;

30

VHDL UP Counter Summary

• PROCESS statement monitors the two inputs clock and reset, which controls the state of the counter.

• A variable count holds the present value of the counter.

• The IF statement evaluates the clock and reset inputs to determine whether the counter should increment or clear.

31

LPM Counters – 1

• The Altera LPM (Library of Parameterized Modules) counter can be used to create counter designs in VHDL.

• This is a structured design approach that uses the LPM-counter as a component in a hierarchy.

• The LPM counter is instantiated in the structured design.

32

LPM Counters – 2

• The basic parameters of the LPM counter, such as width, are defined with a generic map.

• The port map is used to connect LPM counter I/O to the actual VHDL design entity.

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LIBRARY ieee;


LIBRARY lpm;

USE lpm.lpm_components.ALL;

VHDL LPM Library Declaration

• The Altera LPM Library must be added to the usual STD_LOGIC after the ieee library has been declared

34

VHDL LPM Entity• Entity for an 8-bit mod 256 counter.

LPM requires the use of STD_LOGIC data types.

ENTITY simple_lpm_counter IS

PORT(

clk, clear : IN STD_LOGIC;

q : OUT STD_LOGIC_VECTOR (7 downto 0));

END simple_lpm_counter;

35

VHDL LPM ArchitectureARCHITECTURE count OF simple_lpm_counter IS

SIGNAL clrn : STD_LOGIC;--internal signal for active low clr.

BEGIN

-- Instantiate 8-bit counter.

count : lpm_counter

GENERIC MAP (LPM_WIDTH => 8)

PORT MAP (clock => clk,

aclr => clrn,--Intrnal clear mapped to async. clr.

q => q_out (7 downto 0 ));

clrn <= not clear;--Input port inverted mapped to internal clr.

END count;

36

Entering Simple LPM Counters in Quartus II

• Use either the MegaWizard Plug in Manager or manually enter the LPM component.

• Refer to Chapter 9, Entering Simple LPM Counters with the Quartus II Block Editor.

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39

LPM Counter Features – 1

• Parallel Load: A function (syn/asyn) that allows loading of a binary value into the counter FF.

• Clear: asynchronous or synchronous reset.

• Preset: A set (syn. Or asyn.).

40

LPM Counter Features – 2• Counter Enable: A control function that

allows a counter to count the sequences or disable the count.

• Bi-Directional: A control line to switch the counter from a count up to a count down.

41

LPM Counter Features – 3

• There are other features for LPM counters that are given in the Altera Reference Data Sheets.

• The same holds true for other LPM functions, such as arithmetic and memory.

42

4-Bit Parallel Load Counter – 1

• A preset counter (parallel load) has an additional input (load) that can be synchronous or asynchronous and four parallel data inputs.

• The load pulse selects whether the synchronous counter inputs are generated by count logic or parallel load data.

43


• An asynchronous load counter uses an asynchronous clear or preset to force the counter to a known state (usually 0000 or 1111).

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46


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48

Count Enable Logic• As shown in Figure 9.46, adding

another AND gate to each FF input inhibits the count function.

• This has the effect of inhibiting the clock to the counter (a clock pulse has no effect).

• Outputs remain at the last state until the counter is enabled again.

49

Bi-Directional Counter• Adds a direction Input (DIR) to the

counter and the control logic for up or down counting.

• Basic counter element is shown in Figure 9.50.

• The control logic selects the up or down count logic depending on the state of DIR.

50

Terminal Count Decoding – 1• Uses a combinational decoder to detect

when the last state of a counter is reached (terminal count).

• Determines a maximum count out for an UP counter and a minimum for a DOWN counter.

51

Terminal Count Decoding – 2

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53


• The terminal count decoder generates a RCO (ripple carry out) when the terminal count is reached (a high pulse for 1 clock period).

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55

VHDL Counter (8-Bit) – 1 -- Pre-settable_8bit_counter_sync_load

-- 8-bit pre-settable counter with synchronous

-- clear and load and terminal count decoding

-- using STD_LOGIC types

LIBRARY ieee;


USE ieee.std_logic_unsigned.ALL;

56

VHDL Counter (8-Bit) – 2ENTITY presettable_8bit_counter_sync_load IS

PORT(

clk, count_ena : IN STD_LOGIC;

clear, load, direction : IN STD_LOGIC;

p : IN STD_LOGIC_VECTOR (7 downto 0);

max_min :OUT STD_LOGIC;

q : BUFFER STD_LOGIC_VECTOR (7 downto 0));

END presettable_8bit_counter_sync_load;

57

VHDL Counter (8-Bit) – 3 ARCHITECTURE a OF presettable_8bit_counter_sync_load IS SIGNAL terminal_count : STD_LOGIC_VECTOR (8 downto 0);BEGIN PROCESS (clk) -- Since all functions are synchronous only clk is on -- the sensitivity list. BEGIN IF (CLK’EVENT AND clk = ‘1’) THEN IF (clear = ‘0’) THEN -- Synchronous clear. q <= (others => ‘0’); ELSIF (load = ‘1’) THEN – Synchronous load. q <= p;

58

VHDL Counter (8-Bit) – 3 ELSIF (count_ena = ‘1’ and direction = ‘0’) THEN

q <= q –1;

ELSIF (count_ena = ‘1’ and direction = ‘1’) THEN

q <= q+1;

END IF;

END IF;

END PROCESS;

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Terminal Count Code

-- Terminal count decoder (combinational)

Terminal_count <= direction & q;

WITH terminal_count SELECT

max_min <= ‘1’ WHEN “000000000”,

‘1’ WHEN “111111111”,

‘0’ WHEN others;

60

8-Bit Counter Summary – 1

• After the PROCESS statement.

• q = 0 (if clear = 0).

• q = p (if clear = 0 and load = 1).

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• q increments if there is a +’ve clk edge, count_ena = 1, and direction = 1).

• q decrements if there is a +’ve clk edge, count_ena = 1, and direction = 0).

• q remains the same if above conditions are not met.

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63

LPM Counter Functions

• LPM counters can be used as a simple 8-bit counter.

• The component lpm_counter has a number of other functions that can be implemented using specific ports and parameters. These functions are indicated on Table 9.12.

64

LPM Counter VHDL Code – 1-- pre_lpm8

-- 8-bit presettable counter with asynchronous clear and load,

-- count enable, and a directional control port.

LIBRARY ieee;


LIBRARY lpm;

USE lpm.lpm_components.ALL;

65

LPM Counter VHDL Code – 2

ENTITY pre_lpm8 IS PORT( clk, count_ena : IN STD_LOGIC; clear, load, direction : IN STD_LOGIC; p : IN STD_LOGIC_VECTOR (7 downto 0); q_out : IN STD_LOGIC_VECTOR (7 downto 0));END PRE_LPM8;

66

LPM Counter VHDL Code – 3ARCHITECTURE a OF pre_lpm8 IS BEGIN counter 1: lpm_counter GENERIC MAP (LPM_WIDTH => 8) PORT MAP (clock => clk, updown => direction, cnt_en => count_ena, data => p, aload => load, aclr => clear, q => q_out; END a;

67

Shift Register Terminology – 1• Shift Register: A synchronous

sequential circuit that will store and move n-bit data either serially or in parallel in a n-bit Register (FF).

• Left Shift: A movement of data from right to left in the shift register (toward the MSB). One bit shift per clock pulse.

68

Shift Register Terminology – 2

• Right Shift: A movement of data from left to right in the shift register (toward the LSB). One bit shift per clock pulse.

• Rotation: Serial shifting (right or left) with the output of the last FF connected to the input of the first. Results in continuous circulation of SR data.

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Serial Shift Register (SR)

• A 4-Bit Left Shift Register.• DIN is shifted into the LSB FF and shifted

toward the MSB.

Q0 D0

<

DINQ1 D1

<

Q2 D2

<

Q3 D3

< CLK

LSBMSB

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SS Left Shift – 1

Q0 D0

<

DINQ1 D1

<

Q2 D2

<

Q3 D3

< CLK

LSBMSB

73

SS Left Shift – 2

Q0 D0

<

DINQ1 D1

<

Q2 D2

<

Q3 D3

< CLK

LSBMSB

74

SS Left Shift – 3

Q0 D0

<

DINQ1 D1

<

Q2 D2

<

Q3 D3

< CLK

LSBMSB

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SS Left Shift – 4

Q0 D0

<

DINQ1 D1

<

Q2 D2

<

Q3 D3

< CLK

LSBMSB

76

Bi-Directional Shift Register – 1

• Uses a control input signal called direction to change circuit function from shift right to shift left.

• 4-bit bi-directional SR is shown in Figure 9.91.

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Bi-Directional Shift Register – 2• When DIR = 0, the path of Left_Shift_In

is selected.

• When DIR = 1, it selects the Right Shift In Path.

0123 QQQQ

0123 QQQQ

78

SR with Parallel Load

• Similar to a Parallel Load Counter, the Shift Register is shown in Figure 9.93.

• Uses a 2-to-1 Mux (AND/OR) to control inputs to the FF in the SR. The input choice is from the previous FF Output or the Parallel Input.

• When Load = 1, Parallel Data is loaded in on the next clock pulse.

79

Universal SR

• Combines the basic functions of a Parallel Load SR with a Bi-Directional SR.

• Uses Two Control Inputs (S1,S0) to select the function as shown in Figure 9.95.

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Universal SR

81

Universal SR Truth Table (S1/S0)

Function

0 0 Hold Q 3 Q 2 Q 1 Q 0

0 1 Shif t Left RSI * Q 3 Q 2 Q 1

1 0 Shif t Right Q 2 Q 1 Q 0 LSI **

1 1 Load P 3 P 2 P 1 P 0

S 1 S 0 D 3 D 2 D 1 D 0

* RSI = Right-Shif t Input / ** LSI = Left-Shif t Input

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Structured VHDL SR• Structured VHDL Design: A VHDL

design technique that connects predesigned components using internal signals.

• Would use DFF primitives to construct different types such as LSR and RSR.

• A DFF Primitive Port Map is (D, CLK, Q).

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LIBRARY ieee;


LIBRARY altera;

USE altera.maxplus2.ALL;

-- Note: IEEE is before Altera declarations

-- maxplus2 is for the primitive DFF Design

VHDL SR Entity – 1• Basic Entity for a Structural RSR Design

84

ENTITY srg4strc IS

PORT(

serial_in, clk : IN STD_LOGIC;

qo :BUFFER STD_LOGIC_VECTOR(3 downto 0));

END srg4strc;

-- The 4 Bit Register is given a type Buffer to allow

-- Q0 Q3 to be used as Input or Output

VHDL SR Entity – 2• Port description of RSR Entity

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ARCHITECTURE right_shift OF srg4strc IS

COMPONENT DFF

PORT ( d : IN STD_LOGIC;

clk : IN STD_LOGIC;

q : OUT STD_LOGIC);

END COMPONENT;

VHDL SR Component Description• Structural Architecture Component DFF

86

BEGIN

flipflop3: dff

PORT MAP (serial_in, clk, qo(3) );

dffs:

FOR i IN 2 downto 0 GENERATE

flip_flops_2_ to_0: dff

PORT MAP (qo(i + 1), clk, qo(i) );

END GENERATE;

END right_shift;

VHDL RSR Architecture

87

Structured Architecture Example• Four dff components are mapped to

create a RSR, serial_in is to Q3 and shift is toward Q0.

• Uses a FOR GENERATE Loop to create and map the four dff (Flip Flops).

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DataFlow Design Approach

• DataFlow Design: A VHDL design approach that uses Boolean Equations to define relationships between inputs and outputs.

• The Entity is the same as the Structured approach, except the Altera Library is not needed.

• The register q is still declared as a Buffer.

89

ARCHITECTURE right_shift OF srg4dflw IS

SIGNAL d : STD_LOGIC_VECTOR (3 downto 0);

BEGIN

PROCESS(clk)

BEGIN

IF clk’ EVENT AND clk = ‘1’ THEN

q <= d;

END IF;

VHDL Dataflow RSR – 1

• Basic Process Type of Architecture

90

END PROCESS;

d <= serial_in & q(3 downto 1);

END right_shift;

-- The actual data flows on d(0 - 3) outside the process.

-- d(0-3) uses the Concatenate Operator (&) to create

-- the four bit RSR. The process and d assignment are

-- both executed concurrently.

VHDL DataFlow RSR – 2

• Continuation of RSR Architecture

91

PROCESS(clk, clear)

BEGIN

IF clear = ‘0’ THEN

q <= (others => ‘0’); -- asynchronous clear

ELSEIF (clk’EVENT and clk = ‘1’) THEN

Bi-Directional SR VHDL – 1

• Adds a basic direction control to the dataflow architecture given earlier.

92

CASE direction IS

WHEN ‘0’ => q <= q(2 downto 0) & lsi; -- Left Shift

WHEN ‘1’ => q <= rsi & q(3 downto 1); -- Right Shift

WHEN OTHERS => Null;

END CASE;

END IF;

END PROCESS;

END bidirectional_shift;

Bi-Directional SR VHDL – 2• VHDL Architecture Continued

93

Generic Width Shift Register

• Uses a VHDL Generic Clause in the Entity to specify a Width Variable. General form is GENERIC– (Clause := Value)

• For a 4-Bit SR we use GENERIC.– (Width : Positive := 4).

94

ENTITY srt_bhv IS

GENERIC (Width : POSITIVE := 4);

PORT (

serial_in, clk :IN STD_LOGIC;

q : BUFFER STD_LOGIC_VECTOR (width-1 downto 0));

END srt_bhv;

Generic VHDL File Entity

• Width set to 4 Bits

95

ARCHTITECTURE right_shift of srt_bhv IS

BEGIN

PROCESS(clk)

BEGIN

IF(clk’EVENT AND clk = ‘1’) THEN

q(width-1 downto 0) <= serial_in & q(width-1 downto 1);

END IF;

END PROCESS;

END right_shift;

Generic VHDL Architecture

96

LPM Shift Registers• Allows the use of a Programmable LPM

shift register called lpm_shiftreg.

• Has various required and optional parameters that are defined, such as LPM_WIDTH… (Table 9.16 in text).

• Design approach is the same as for Counters using Structured VHDL.

97

ENTITY srg8_lpm2 IS

PORT(

clk :IN STD_LOGIC

serial_in :IN STD_LOGIC;

serial_out :OUT STD_LOGIC);

END srg8_lpm2;

LPM Entity Statement• Remember to declare lpm Library for use

98

ARCHITECTURE lpm_shift OF srg8_lpm2 IS

BEGIN

Shift_8 : lpm_shiftreg

GENERIC MAP (LPM_WIDTH => 8,

LPM_DIRECTION => “RIGHT”)

PORT MAP (clock => clk,

shiftin => serial_in,

shiftout => serial_out);

END lpm_shift;

LPM SR Architecture

99

Shift Register Counters

• Two types: Ring and Johnson• Ring Counter: A serial Shift Register

with feedback from the output of the last FF to the input of the first FF.

• Counter sequences are based on a continuous rotation of data through the SR.

100

Ring Counters – 1

• A basic Ring Counter (Figure 9.102) is constructed of D-FF with a Feedback Loop.

• Data is initially loaded into the SR by using either Resets or Presets.

• The counter can circulate a 0 or 1 by loading a 1000 or 0111.

101

Ring Counters – 2

• The Modulus of a Ring Counter is defined as the maximum number of unique states.

• Modulus is dependent on the initial load value {1000, 0100, 0010, 0001} = Mod4 while {1010, 0101} = Mod2.

• Typically an N-FF Ring Counter has N-States, not 2N like a binary counter.

102

Johnson Counters – 1• Johnson Counter: A serial shift register

with the complemented feedback from the output of the last FF to the input of the first FF.

• Same as the Ring Counter sequences based on a continuous rotation of data through the SR.

103

Johnson Counters – 2• Same as a Ring (Figure 9.106) except

that (Complement) is fed back to D3, not to Q0.

• Adds a complement or “twist” to the data and is called a Twisted Ring Counter.

• Usually Initialized with 0000 by a Clear.

0Q

104

Johnson Counters – 3• Typically has more states than a ring

counter.• Sequence of states = {0000, 1000,

1100, 1110, 1111, 0111, 0011, 0001}.• Maximum Modulus is 2n for a circuit with n flip-flops.

chapter 9 counters and shift registers. 2 counter: a sequential circuit that counts pulses. used for...

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