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5/25/2018 [123doc.vn] - KIEN TRUC MAY TINH - Mot So Kien Truc Tap Lenh

1/31

Mt s kin trctp lnh

HUST-FET, 13/02/201151Chng 2. Ngnng my tnh v cc php ton


2/31

Kin trc RISC

Reduce Instruction Set Computer

DEC Alpha,AMD 29k,ARC,ARM,Atmel AVR, MIPS, PA-RISC,

Power(PowerPC), SuperH, v SPARC. nh dng lnh v dilnh c nh, n gin

D gii mlnh

Cc thanh ghi chungmc ch cth s dng trongnhiu ng cnh D thit k phn mm bindch

Cth cn cc thanh ghidu phy ng ringbit

Ch a ch n gin Ccch a ch phc tp c thc hin thng quachui lnh s

hc vlnh np/ghi

th tr ccloi d liu phc tp

http://en.wikipedia.org/wiki/DEC_Alphahttp://en.wikipedia.org/wiki/AMD_29khttp://en.wikipedia.org/wiki/ARC_Internationalhttp://en.wikipedia.org/wiki/ARM_architecturehttp://en.wikipedia.org/wiki/Atmel_AVRhttp://en.wikipedia.org/wiki/MIPS_architecturehttp://en.wikipedia.org/wiki/PA-RISChttp://en.wikipedia.org/wiki/Power_Architecturehttp://en.wikipedia.org/wiki/PowerPChttp://en.wikipedia.org/wiki/SuperHhttp://en.wikipedia.org/wiki/SPARChttp://en.wikipedia.org/wiki/SPARChttp://en.wikipedia.org/wiki/SuperHhttp://en.wikipedia.org/wiki/PowerPChttp://en.wikipedia.org/wiki/Power_Architecturehttp://en.wikipedia.org/wiki/PA-RISChttp://en.wikipedia.org/wiki/PA-RISChttp://en.wikipedia.org/wiki/PA-RISChttp://en.wikipedia.org/wiki/MIPS_architecturehttp://en.wikipedia.org/wiki/Atmel_AVRhttp://en.wikipedia.org/wiki/ARM_architecturehttp://en.wikipedia.org/wiki/ARC_Internationalhttp://en.wikipedia.org/wiki/AMD_29khttp://en.wikipedia.org/wiki/DEC_Alpha


3/31

Kin trc CISC

Complex Instruction Set Computer

System/360, z/Architecture, PDP-11, VAX, Motorola 68k, v x86.

Lnh c di thayi, phc tp Cth baogm 1 vi php tonnh

Gn ngnng lp trnhbc cao

Nhiu ch a ch phc tp

H tr ccloi d liu phc tp

http://en.wikipedia.org/wiki/System/360http://en.wikipedia.org/wiki/Z/Architecturehttp://en.wikipedia.org/wiki/PDP-11http://en.wikipedia.org/wiki/VAXhttp://en.wikipedia.org/wiki/Motorola_68000_familyhttp://en.wikipedia.org/wiki/X86http://en.wikipedia.org/wiki/X86http://en.wikipedia.org/wiki/Motorola_68000_familyhttp://en.wikipedia.org/wiki/VAXhttp://en.wikipedia.org/wiki/PDP-11http://en.wikipedia.org/wiki/PDP-11http://en.wikipedia.org/wiki/PDP-11http://en.wikipedia.org/wiki/Z/Architecturehttp://en.wikipedia.org/wiki/System/360


4/31

CISC vs. RISC


RISC CISC

-Tp ln cc thanh ghi-Tp lnh n gin

-Tp trung traoi d liu gia thanh ghi

- Cclnh thc hin trong mt chuk my

- Cclnh LOAD/STORE n gin truy

cp b nh

-Gii hn ch a ch

-T m cchiu dic nh

-Gii hn s thanh ghi-Tp lnh phc tp

-Nhn mnh vo cchot ng truycp

b nh

-Lnh cth c thc hin trong nhiu

chuk my

-Mt lnh cth tng ng vi nhiu

lnh ca RISC

-Nhiu ch a ch

- Mlnh cchiu di thayi ty votng lnh


5/31

CISC vs. RISC


RISC CISC

- Mlnh thc hin nhanh

-n v iu khin n gin

-Gii m nhanh

-X l song songng ng hiu sut cao

-Thit k, phttrin vkim tra nhanh-H tr trnhdch tng cng s ti u

-Gim ccli r nhnhca ng ng

-Tng tc truyn thams cho ccth tc

- Ngnng lp trnh assembly mnh

-Gim cc yucu khithit k trnhdch

- Cc tnhnng vi du phy ng mnh

-Tng kh nng ca cache


6/31

Vd 2.4. So snhhiu nng RISV vs. CISC

Kin trctp lnh ISA c 2 lp ch th phc tp (C) vn gin (S).Trong 1 chng trnhthi gianthc hin ch th S chim 95%. trin

khai ISA bng kin trc RISC tas trin khai ccch th S bng phncng vch th C bng phn mm (dngon ch th S v coinh 1 chth gi C). So snhvi kin trc CISC, ccch th S s c thc hinnhanhhn 20% v ccch th CISC b chm i 3 ln. Kin trc no chiu nng cao hn v cao hn bao nhiuln?



7/31

Kin trctp lnh MIPS

nh dng ch th:32 bit

3 loi nh dng:R-ch th thanh ghi: 2 tonhng ngun thanh ghi, 1 tonhng

ch thanh ghi

I-ch th trc tip: 1 tonhng ngun thanh ghi, 1 tonhng

ngun trc tip, 1 tonhng ch thanh ghiJ-ch th nhy: 1 tonhng ngun trc tip


op

op

op

rs rt rd sa funct

rs rt immediate

jump target

R format

I format

J format


8/31

Nguyntc thit k MIPS (RISC)


Tnhn gin quantrng hn tnh quytc(Simplicity favors regularity)Ch th kchthc c nh (32 bit)

tnh dng ch th (3 loi nh dng) Mlnh v trc nh (6 bit u)

Nh hn th nhanhhnS ch th gii hn

S thanh ghigii hn

S ch a ch gii hn

Tng tc cctrng hp thngdng Cc tonhng s hc ly t thanh ghi (my tnhda trnc ch load-

store)

Ccch th cth cha tonhng trc tip

Thit k tt i hi s tha hip 3 loi nh dng ch th


9/31

Ch th s hc ca MIPS

HUST-FET, 13/02/201159

Mhp ng ca ch th s hc

add $t0, $s1, $s2sub $t0, $s1, $s2

Mi ch th s hc thc hinmt php ton

Mi ch th cha chnh xc bach s ca cc thanh ghitrong tp thanh ghica ng d liu ($t0,$s1,$s2)

destination source1 op source2

nh dng ch th loi thanh ghi (R format)

0 17 18 8 0 0x22


10/31

Cctrng trong ch th MIPS


Cctrng trong 1 ch th MIPS c t tn:

op rs rt rd shamt funct

op 6-bits mlnh xcnh php ton (opcode)rs 5-bits ch s thanh ghicha tonhng ngun 1 trong

tp thanh ghi

rt 5-bits ch s thanh ghicha tonhng ngun 2 trongtp thanh ghi

rd 5-bits ch s thanh ghis lu kt qu trong tp thanh ghishamt 5-bits s lng dch (choch th dch)

funct 6-bits mchc nng thm chophn mlnh


11/31

Tp thanh ghica MIPS


Register File

src1 addrsrc2 addr

dst addr

write data

32 bits src1data

src2data

32locations

32

5

32

5

5

32

write control

Gm 32 thanh ghi 32-bit

2 cng c 1 cng ghi

Thanh ghi: Nhanhhn b nh chnh

- Nhiu thanh ghis chm hn

(VD., 1 tp gm 64 thanh ghi word s

chm hn tp gm 32 thanh ghikhong 50%)

- S lng cng c ghinh hng bc 2 n tc

D bindch

- VD., (A*B) (C*D) (E*F) cth thc hin php nhn theotht bt k, khngging nh ngn xp

Cha bin chng trnh- ci thin ln mchng trnh


12/31

Cc thanh ghi MIPS


Tn Ch s Cngdng Preserveon call?

$zero 0 constant 0 (hardware) n.a.

$at 1 reserved for assembler n.a.

$v0 - $v1 2-3 returned values no

$a0 - $a3 4-7 arguments yes

$t0 - $t7 8-15 temporaries no$s0 - $s7 16-23 saved values yes

$t8 - $t9 24-25 temporaries no

$gp 28 global pointer yes

$sp 29 stack pointer yes$fp 30 frame pointer yes

$ra 31 return addr (hardware) yes


13/31

Truycp b nh


2 ch thdch chuyn d liu truycp b nh

o lw $t0, 4($s3) #c 1 t t b nho sw $t0, 8($s3) #ghi 1 t vo b nh

D liu c c vo (lw) hoc ghi rat (sw) 1 thanh ghitrong tp thanh ghi 5 bit ch s thanh ghi

32 bit a ch b nh c to rabng cchcng gitrthanh ghic s (base register) vi gitr offsetTrng offset rng 16 bit s gii hn cc nh trong khong 213

hay 8,192 words (215

hay 32,768 bytes) tnht gitr ca thanhghic s


14/31

nh dng lnh truycp b nh


nh dng ch th Load/Store (nh dng I):lw $t0, 24($s3)

35 19 8 2410Memory

data word address (hex)0x000000000x000000040x000000080x0000000c

0xf f f f f f f f

$s3 0x12004094

2410 + $s3 =

. . . 0001 1000+ . . . 1001 0100

. . . 1010 1100 =

0x120040ac

0x120040ac$t0


15/31

Vd 2.5. Truycp bng (array)

HUST-FET, 13/02/201165

Cho A[ ] = l 1 mng bt u ti a ch c s lu trongthanh ghi $s3;

Bin h c gn vi thanh ghi $s2; Dch: A[5] = h + A[8]

Thnh mhp ng MIPS:

lw $t0, 32 ($s3) # $t0 A[8]

add $t0, $s2, $t0 # $t0 h+$t0

sw $t0, 20 ($s3) # A[5] $t0

OP rs rt immediateI-type

8765432

1


16/31

Vd 2.6. Truycp mng vi ch s thayi

HUST-FET, 13/02/201166

A[ ] = array with base address in $s3;

variables g, h, iassociated with registers $s1, $s2, $s4

Compile: g = h + A[i]

into MIPS instructions:

add $t1, $s4, $s4 # $t1 i+i = 2i

add $t1, $t1, $t1 # $t1 2i+2i = 4i

add $t1, $t1, $s3 # $t1 address of A[i]

lw $t0, 0 ($t1) # $t0 A[i]

add $s1, $s2, $t0 # $s1 h + A[i]


17/31

Lu tr byte: Endianess (Nhc li)

HUST-FET, 13/02/201167

Big Endian: leftmost byte is word address

Little Endian: rightmost byte is word address

Thanh ghi lsb

3 2 1 0

a ch:little end ian by te 0

0 1 2 3

a ch:bigend ian by te 0

msb


18/31

c v ghi byte

HUST-FET, 13/02/201168

MIPS cclnh c bit dch chuyn byteslb $t0, 1($s3) #load byte from memory

sb $t0, 6($s3) #store byte to memory

op rs rt 16 bit number

Cc byte 8bit noc c v ghi?Lnh c a byte c c vo 8 bit ngoi cng bn

phi t b nh vo thanh ghich- Cc bit khcca thanh ghi?

Lnh ghily 8 bit ngoi cng bnphi ca thanh ghingun v ghi vob nh

-Gi cc byte khc trong t nh khng thayi


19/31

Vd 2.7.c ghi byte

HUST-FET, 13/02/201169

Cho on m sau vtrng thib nh. Xcnhtrng thib nh sau khithc hin on m

add $s3, $zero, $zero

lb $t0, 1($s3)

sb $t0, 6($s3)

Memory

0x 0 0 9 0 1 2 A 0Data Word

Address (Decimal)

0

4

8

12

16

20

24

0x F F F F F F F F

0x 0 1 0 0 0 4 0 2

0x 1 0 0 0 0 0 1 0

0x 0 0 0 0 0 0 0 0

0x 0 0 0 0 0 0 0 0

0x 0 0 0 0 0 0 0 0

Gitr lu trong $t0?

iu gxy ra khi my tnh lloi littleEndian?

T noc ghi vob nh v trno?

hi


20/31

c ghina t

HUST-FET, 13/02/201170

MIPS also provides special instructions to movehalf words

lh $t0, 1($s3) #load half word from memory

sh $t0, 6($s3) #store half word to memory

op rs rt 16 bit number

What 16 bits get loaded and stored? load half word places the half word from memory in the

rightmost 16 bits of the destination register- what happens to the other bits in the register?

store half word takes the half word from the rightmost16 bits of the register and writes it to the half word inmemory

- leaving the other half word in the memory word unchanged

L h t ti


21/31

Lnh trc tip


addi $sp, $sp, 4 #$sp = $sp + 4

slti $t0, $s2, 15 #$t0 = 1 if $s2


22/31

Lnh dch


Shifts move all the bits in a word left or right

sll $t2, $s0, 8 #$t2 = $s0 > 8 bits

Instruction Format (R format)

Such shifts are called logical because they fill withzeros Notice that a 5-bit shamt field is enough to shift a 32-bit value

25 1 or 31 bit positions

0 16 10 8 0x00

L h l i


23/31

Lnh logic


There are a number of bit-wise logical operations in theMIPS ISA

and $t0, $t1, $t2 #$t0 = $t1 & $t2

or $t0, $t1, $t2 #$t0 = $t1 | $t2

nor $t0, $t1, $t2 #$t0 = not($t1 | $t2)

Instruction Format (R format)

andi $t0, $t1, 0xFF00 #$t0 = $t1 & ff00

ori $t0, $t1, 0xFF00 #$t0 = $t1 | ff00

Instruction Format (I format)

0 9 10 8 0 0x24

0x0D 9 8 0xFF00

S d h l


24/31

S dng cchng s ln

HUST-FET, 13/02/201174

a 1 hng s 32 bit vo 1 thanh ghi

S dng 2 lnh: Lnh np vophn cao "load upper immediatelui $t0, 0xaaaa

Lnh np vophn thp:

ori $t0, $t0, 0xaaaa

16 0 8 1010101010101010

1010101010101010

0000000000000000 1010101010101010

0000000000000000

1010101010101010 1010101010101010

L h i khi d h t h


25/31

Lnh iu khin dngchng trnh


Lnhr nhnh ciu kin:

bne $s0, $s1, Lbl #go to Lbl if $s0$s1beq $s0, $s1, Lbl #go to Lbl if $s0=$s1

Ex: if (i==j) h = i + j;

bne $s0, $s1, Lbl1add $s3, $s0, $s1

Lbl1: ...

nh dng lnh (nh dng I):

0x05 16 17 16 bit offset

a ch n c xcnh nh th no ?

X h h h h


26/31

Xcnh a ch r nhnhn

HUST-FET, 13/02/201176

S dng 1 thanh ghi (ging nh lw v sw) cng vi 16-bit offset Thanh ghia ch lnh PC (Instruction Address Register )

- Vic s dng PC c t ng bao hm trong lnh- PC c cp nht (PC+4) khilnh cnp vvy khi tnh ton ncha gi

tr a ch ca lnh k tip

gii hn khong cchr nhnh trong khong -215 n +215-1 (word) lnhk t lnh saulnh r nhnh. Tuy nhinphn ln ccr nhnh laphng.

PCAdd

32

32 3232

32

offset

16

32

00

sign-extend

Trng 16 bit thp ca lnh r nhnh

branch dstaddress

?Add

4 32

S h h t l h h h


27/31

So snhh tr lnh r nhnh

HUST-FET, 13/02/201177

Clnh beq, bne, ccloi iu kin khc? (VD., r nhnhnu nh hn)? Cn 1 lnh so snh khc: slt

Set on less than:slt $t0, $s0, $s1 # if $s0 < $s1 then

# $t0 = 1 else

# $t0 = 0

Instruction format (R format):

Cc phinbn khcca slt

slti $t0, $s0, 25 # if $s0 < 25 then $t0=1 ...

sltu $t0, $s0, $s1 # if $s0 < $s1 then $t0=1 ...

sltiu $t0, $s0, 25 # if $s0 < 25 then $t0=1 ...

0 16 17 8 0x24

S dng slt


28/31

S dng slt

HUST-FET, 13/02/201178

Dng slt, beq, bne, v gitr 0 trong thanh ghi $zeroto ra cciu kin r nhnh khc

less than blt $s1, $s2, Label

less than or equal toble $s1, $s2, Label

greater than bgt $s1, $s2, Label

great than or equal to bge $s1, $s2, Label

Cclnh r nhnhc thm votp lnh nh cclnh

gi, c nhn dng vm rng bng trnhdchassembler Trnhdch assembler cn thanh ghi ring ($at)

slt $at, $s1, $s2 #$at set to 1 if

bne $at, $zero, Label #$s1 < $s2

Lnh nhy khng iu kin


29/31

Lnh nhy khngiu kin

HUST-FET, 13/02/201179

Lnhnhy khngiu kin:

j label #go to label

nh dng lnh (J Format):

0x02 26-bit address

PC4

32

26

32

00

t trng 26 bits thp ca lnh nhy

Nhy n a ch xa


30/31

Nhy n a ch xa

HUST-FET, 13/02/201180

Khia ch nhy n xahn, v khngth biu dinbng 16 bits?

Phn mm assembler h tr n chn 1 lnh nhy khngiu kin n a ch nhy n vo iu kin r nhnh

beq $s0, $s1, L1

tr thnh

bne $s0, $s1, L2

j L1L2:

Nhy n a ch thay i


31/31

Nhy n a ch thayi

Cc ngnng bc cao c cclnh nh casehay switch cho phpla chn trong nhiutrng hp ph thuc vo 1 bin

Lnh:jr $t1 #go to address in $t1

M my:

op rs funct

0 9 0 0 0 8 = 0x08

R format

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