presentation on characterization of a wlan...

This document is owned by Agilent Technologies, but is no longer kept current and may contain obsolete or

inaccurate references. We regret any inconvenience this may cause. For the latest information on Agilent’s

line of EEsof electronic design automation (EDA) products and services, please go to:

www.agilent.com/fi nd/eesof

Agilent EEsof EDA

nstewart

Text Box

Presentation on Characterization of a WLAN Transceiver

1

Group/Presentation Title

July 24, 2007Page 1

Increased Insight with Increased

Characterization of a WLAN Transceiver

Agilent EEsof EDA

Andy Howard Applications EngineerJuly 24, 2007

2


July 24, 2007Page 2

Objectives

• Show how GoldenGate makes block-level design easier

• Show that GoldenGate is able to handle much more thanindividual blocks

• Show GoldenGate’s capacity, that enables extracted view and statistical simulations you might have considered impossible

• Show GoldenGate’s ability to simulate large extracted viewswith modulated signals

This presentation shows that with GoldenGate it is easy to setup and run common block-level simulations and that GoldenGate is able to handle large, complex simulations in a reasonable amount of time. Because of these capabilities, designers should run larger extracted view (beyond just the block level) and Monte Carlo simulations, as well as simulations with modulated signals rather than just sinusoids.

3


July 24, 2007Page 3

Outline

Block-level design flow

Applying GoldenGate in block-level design of LNA, mixer, oscillator, amplifier, etc.

Post-layout simulations, with and without Monte Carlo

System-level simulations – combining blocks together

Sinusoidal inputs, effect of blockers, modulated signals –Where does degradation occur along the signal path?

Investigating manufacturing variations – show capacity

Initially, we will discuss a typical block-level design flow. Next we will show a number of examples applying GoldenGate in block-level design. We will show extracted view simulations and the use of Monte Carlo to investigate design variability. Most simulations are with sinusoid inputs, but some have modulated signals, which are necessary to see whether the system meets its actual specifications.

4


July 24, 2007Page 4

Block-level design flow

Meetspecs?

Run parameter sweeps,try different topologies

Create layout, extract parasitics, re-simulate

Meetspecs?

Run statisticalsimulations

Meetspecs?

Simulate multiple blocks together, check system-level performance (ACPR, EVM, BER, etc.)

Specs for each block from system designer (but may be “dumbed down” due to limitations of some simulators)

YES

YES

NO NONO

YESNO

YES

This is a typical block-level design flow, except that we doubt many designers are simulating multiple blocks together, after parasitic extraction, and with modulated signals. GoldenGate makes these more advanced simulations possible. EVM simulation of OFDM signals requires the use of Ptolemy. A suggested procedure is written in a Knowledge Center document, #296766, and involves exporting a modulated signal from Ptolemy to a file, reading it into a GoldenGate simulation, then running another Ptolemy simulation to read in the results from the GoldenGate simulation and compute the EVM.BER simulation would also require the use of Ptolemy.

5


July 24, 2007Page 5

Implications for the simulator

• Simulations that yield specifications directly should be easy tosetup and run

• Displaying results to enable design trade-offs should be easy

• Large simulation capacity necessary to handle extracted viewsand Monte Carlo quickly

To enable this design flow, the simulator should have (at least) these characteristics.

6


July 24, 2007Page 6

WLAN transceiver block diagram

Typical block level specifications:gain, gain compression, noise figure, tuning range, phase noise, output power, IP3, power consumption, blocker attenuation, sensitivity to temperature, frequency response, noise levels, etc.System level specifications: EVM, ACPR, BER, etc.

This shows a block diagram of a WLAN transceiver that was designed using a generic Cadence PDK. We have an RFIC Flow Workshop that includes the details of simulating each of the blocks within this transceiver. Due to time limitations, this seminar will include just some of the simulations that you could carry out. System level specifications may be simulated as well. However, BER will require the use of Ptolemy, and EVM simulation of certain types of signals will also require Ptolemy.

EVM = error vector magnitudeACPR = adjacent channel power ratio (a specification for some

systems)BER = bit error ratio

7


July 24, 2007Page 7

LNA design - determining optimal source impedance for minimum noise figure

Most of the simulations shown are for characterizing blocks that are complete or nearly complete. This setup is for simulating a portion of the LNA (low-noise amplifier) to determine the optimal source impedance for minimum noise figure, a step you would carry out early in the design process. Noise circles, available gain circles and the source stability circle are plotted for the frequency selected by moving marker m2. GoldenGate is promoted more as a verification tool to be used near the end of the design flow. However, it may be used just as easily and effectively early in the design process as well.

8


July 24, 2007Page 8

LNA simulations

Part of LNAsubcircuit, withDC back-annotation

This shows a simulation setup for the LNA. The subcircuit shows the back-annotation of DC voltages to the schematic.

9


July 24, 2007Page 9

LNA S-parameters and noise

Turning on device noise contribution listing output

Device noise contribution listing output

If you have never seen GoldenGate before, it is an alternative simulator within the Cadence Analog Design Environment window. There are several different analysis types, depending on what performance specifications you want to see. “SP” is for S-parameter and small-signal noise analysis. We are sweeping the input frequency, although you could sweep otherparameters. The noise contribution listing shows that the thermal noise from the two primary amplifying FETs in the middle of the LNA are the main sources of noise.

10


July 24, 2007Page 10

Noise figure and gain versus frequency

This shows the GoldenGate tool qWave displaying S21 and the noise figure. The Cadence tools such as Wavescan could be used for displaying these results, or since GoldenGate will now write ADS or RFDE dataset files, you may also use the data display. If you have existing data display files, they may be used to display GoldenGate simulation results, although with some editing required.

11



1-dB power gain compression setupGC is a harmonic balanceanalysis specifically for computing power gain compression

Specify input source and output probeSpecify amount of compression in dB

Specify input power range

Gain compression is another important characteristic of the amplifier. “GC”is an analysis that computes an n dB power gain compression point that you specify. You have to estimate an input power level at which the amplifier should be operating linearly. Other than that the simulation setup is pretty simple.

12



Computing results

These functions are specific to the GC analysis

Return output power at1-dB gain compression,Gain in linear region,Input power at gain compression pointResults output automatically when simulation finishes

GoldenGate knows the type of analysis you are running and lists the functions you may use (for post-processing the simulation results) that correspond to that analysis. Many analyses output results without requiring you to use equations at all.

13



Plot showing gain compression

This plot shows the gain compression and what the output power would be if there where no gain compression.

14



If you want voltage gain and gain compression

Use CR analysis and sweep input power, “pin”

Both power and voltage gain may be computed

If you want voltage gain compression, use “CR” analysis and a sweep of the input power. Here voltage gain is defined as the ratio of the voltage at the load to the voltage at the input to the amplifier. The power gain may be computed as well, as the power delivered to the load minus the power available from the source. Using ports and virtual probes (preferred over goldenGateLib probes because they don’t modify the schematic) along with equations enable you to compute exactly what you want.

15



Simulation results

Voltage gain compression may be computed in Data Display

Power and voltage gains both output

This shows the simulation results output to the log file and the voltage gain compression at the output plotted versus the available source power, pin in dBm, and versus the output voltage in dB. Interpolation has been used in this data display plot to obtain finer resolution than the actual step size used in the sweep. Other simulations could be run on the LNA, including Monte Carlo, extracted views, IP3, etc., but we will move on to other blocks.When running a sweep, if you have performances defined or if an analysis outputs data automatically, the output log is updated after each sweep point. This enables you to see the simulation progress, and you may terminate it early if poor performance indicates a potential simulation setup mistake.

16



Mixer noise figure

RF In Baseband Out

analogLib ideal_balun

LO DC biasLO voltage source

This scheme is OK if no DC bias is needed

This shows a setup for simulating the mixer noise figure and conversion gain. This setup will be OK if there is no need to supply a DC bias at the input or output. Also, it assumes common-mode signals are insignificant.

17



Mixer noise figure simulation setupSSNA is a harmonic balance analysis specifically for noise

Specify LO tone

Specify output probe and output signal indices

Specify noise figure type

Specify small-signal input tone

It would be difficult to set this up incorrectly!

SSNA is an analysis that is specific for noise figure simulation in circuits with large signal(s). The large signal could be an LO or a blocker, for example. This setup is very straightforward.With IEEE noise figure, NF is calculated assuming the signal is present only on one side of the LO, and only noise at this frequency is considered in the calculation (unlike SSB NF, where noise at the image frequency is also considered, as well as noise from the LO harmonics.) During thecomputation of total noise at the output, the input source(s) contribute noise at the input frequency only. In IEEE noise figure, added noise is equal to total noise minus input noise, but this is not true with SSB NF.

18



Mixer noise figure simulation results

Various gains, noise figure, and other noise data are output by the simulator automatically.

Various gains and noise voltages are output by the simulator automatically without requiring you to write equations.“noise in” is the noise at the output due only to the noise of the input source. “noise out” is the total noise at the output.“added_noise” is the noise created by the circuit, excluding the input sourcecontribution.

19



Noise figure and conversion gain versus LO amplitude

Can sweep other parameters easily

Sweeping 14 values of LO amplitude required 13 seconds.

This qWave plot shows the noise figure and conversion gain versus the LO amplitude. Clearly if this amplitude is too low, the mixer performance degrades. You may sweep other parameters easily and would want to during the design process to find optimal performance.

20



Mixer IP3IP is a harmonic balanceanalysis specifically for computing intercept points

Specify:circuit type, IP Rank, power or voltage, input and LO (if a mixer) frequencies, source and output probe

It would be difficult to set this up incorrectly!Fast IPN works only with IP Rank 3

IP analysis is specifically for computing intercept points, and works for voltage and power as well as amplifiers and mixers. With Fast IPN, one of the two RF or IF input tones is treated as a small signal. This means one less large signal tone than normal IP analysis is required. The simulation runs faster and uses less memory, with the tradeoff being a slight loss in accuracy.

21



Mixer IP3 outputs

Linear extrapolation of IP3 point

This shows the graphically-extracted output IP3 point.

22



Mixer conversion gain compressionUse CR analysis for voltage conversion gain compression, GC for power conversion gaincompression

This simulation is for determining voltage conversion gain compression. The input- and output-referred IP3 points are computed from the desired output tone and undesired intermodulation tone at the lowest input signal level and the small-signal voltage conversion gain, so you can get IP3 and conversion gain from the same simulation. This data display may be re-used for other mixer simulations, so you don’t have to re-enter the equations and plots. The X-axis variable, Vin_dB, in the lower right plot is the differential voltage at the input to the mixer and is the voltage used in the conversion gain calculation. The X-axis variable, VRFamp_dB, in the upper left plot is the swept variable in the simulation and is the voltage of the internal source in the RF input port shown on slide 16. VRFamp_dB will only be the same as Vin_dB if the input impedance of the mixer is equal to the port resistance.

23



VCO simulationCommon RFIC oscillator topology

S-parameters fromMomentum simulation of spiral

Varactor diodes

We will analyze the voltage-controlled oscillator next. This simulation uses S-parameter data, which was generated by a Momentum (a 3-D planar electromagnetic simulator) simulation of the spiral inductor layout. There are several analyses (resonator impedance versus frequency and tuning voltage, active circuit impedance versus signal amplitude, etc.) you would want to carry out before simulating the VCO, but these are not shown due to time limitations.

24



Checking for instability

Eigenvalue Computation is preferred, but Nyquist must be used if circuit contains S-parameter model(s)

A single unstable frequency is found,as expected

May run stability analysis on non-oscillator circuits, also.

An initial oscillator test is to verify that the circuit is unstable at the desired frequency of oscillation and at no other frequencies. This Stability Analysis is an option under DC analysis, and may be carried out on other circuits such as amplifiers to check for (undesired) frequencies of oscillation.

25



Steady-state behavior versus tuning voltageRun CR analysis with Oscillator Analysis specified. Varactor tuning voltage swept.Fosc is the approximate frequency of oscillation.

Tuning sensitivity computed with diff()

Oscillator analysis is carried out as an option under CR analysis. The varactor diode tuning voltage is swept to tune the frequency of oscillation, which is plotted. The finite difference function, diff(), is used to compute the derivative of this frequency-versus-tuning-voltage curve. GoldenGate has a number of performance expressions for computing various results from the simulation. If you specify that a dataset be created so you may plot the results using the ADS/RFDE data display, then you may do further post-processing using the data display expressions. But from within data display, you cannot use the GoldenGate performance expressions.

26



Compute phase noise

Noise contribution table data output for each offset frequency

This shows phase noise simulation results as well as a noise contribution listing at the 100 kHz offset frequency. Flicker noise from several PMOS devices at the core of the oscillator is the primary contributor to the phase noise.

27



Simulating LNA and mixer together

Noise figure, IP3, gain, and gain compression

LO source uses NoiseCor to re-use spectrum and noise from VCO and prescaler simulation

Small-signal noise analysis results

Now we will simulate the LNA and mixer together before going on to simulate the whole receiver and transmitter. We will simulate the combined noise figure, IP3, gain, and gain compression. A NoiseCor is used to re-use the VCO phase noise data in this noise figure analysis. The overall noise figure is about 4.3 dB. This is significantly higher than the ~1 dB noise figure of the LNA, but better than that of the mixer by itself.An advantage of being able to simulate multiple blocks together is that you get a more accurate prediction of performance because the interaction between blocks is handled more accurately. Instead of presenting an ideal, fixed resistance to the mixer, we are now presenting the output of the LNA, which certainly varies with frequency.

28



Simulating IP3 of LNA and mixerUses same schematic.Uses CR analysis to compute voltage IP3 points

Simulation run at two input power levels to verify slopes of fundamental and intermod tones

This IP3 simulation uses CR analysis and several performances. The input power level is stepped to be sure the slopes of the desired and intermodulation tones are correct for the extrapolation of the IP3 point. The input-referred IP3 point is computed by subtracting the voltage conversion gain from the output-referred IP3 point.

29



IP3 simulation results

These slopes arecorrect (1dB/dB and 3dB/dB) so graphicalextrapolation of IP3point is valid

This shows the desired fundamental tone at the output as well as the undesired intermodulation distortion term. The slopes are correct. To speed up this simulation, you could run it at just the lower input power level and occasionally run a swept power simulation to verify that the mixer is far from compression. This may be determined by measuring the slopes or if the input and output IP3 points and conversion gains are the same at the two lowest input power levels.

30



Gain compression

Run previous simulation, sweeping input power high enough to cause gain compression

Voltage gain compression may be simulated from the same setup, just sweeping the input power high enough to cause gain compression. The IP3 points may be obtained from the data when the input power is at its lowest level. The gain compression point will be different if you have only one input tone rather than two. You could treat one of the input tones as a blocker and see how its amplitude and frequency affect the compression point.

31



Conversion gain and noise figure of extracted view, with Monte Carlo

100 Monte Carlo trials required about 31 minutes(single CPU)

50,870 netlist elements, 371 Mbytes total memory required

The simulations up until now have been of schematic views. Now we want to investigate the degradation in performance when parasitic elements are included as well as variation in performance when the device model statistical variation is included. This Monte Carlo simulation indicates a significant reduction in the voltage conversion gain, from 31 dB to an average value of about 23.8 dB. Also, the mean noise figure is about 2 dB higher than the schematic-view value. Based on the variation shown, if you needed a 30 dB voltage conversion gain, for example, your yield would not be very good.

32



Correlation dataIndicates which process statistical variables have the biggest effect on circuit performances

The upper right tables show (in order) the correlations between the statistical variables and the two performances, voltage gain and noise figure. The scatter plots show that as cjmim increases, the voltage gain decreases and that the voltage gain and noise figure are better for lower values of rshhip. If you have the ability to shift these variables, the scatter plots indicate the direction they should be shifted.

33



Output IP3 and conversion gain of extracted view, with Monte Carlo

100 Monte Carlo trials required about 115 minutes(single CPU)

This shows the IP3 and conversion gain statistical results. The conversion gain distribution is about the same. The variation in output IP3 is relatively small.

34



Receiver, LNA, 2 mixers, frequency divider, 2 analog baseband chains, extracted view

64,931 netlist elements,1475 nonlinear models

Small-signal source

Noise figure and small-signal conversion gain100 Monte Carlo iterations required 6.5 hours w/LSF(could be reduced with all CPUs=fastest in cluster.)

LNA

Frequency divider

LO source, re-uses VCO data via Noisecor file

This simulation was run on more of the receiver, including two mixers, two baseband receive chains, and the frequency divider. The simulation was a test of GoldenGate’s capacity. The Monte Carlo analysis could be completed more quickly with faster computers in the LSF cluster or with more computers in the cluster.

35



Receiver, LNA, 2 mixers, frequency divider, 2 analog baseband chains, extracted view

64,934 netlist elements,1475 nonlinear models

WLAN input signal, requires 51 minutes and 54 secondsfor 8192 time points. 408 Mbytes total memory.

LNA

Frequency divider

LO source, re-uses VCO data via Noisecor file

WLAN Source,reads I and Q data

This was a simulation of the same circuit, but with WLAN baseband input sources and without Monte Carlo.

36



Transmitter compression simulation

RF Out

Q Baseband In

Power Amp

I Baseband In

BalunFreq Div

1 MHz sines

LO at 2.611 GHz

Up to this point we have run simulations of the receiver. We could re-run similar simulations on the blocks in the transmitter, but due to limited time available in this seminar, we will just show results from simulations of the overall transmitter. The initial simulation is of gain compression of the transmitter. If the baseband I and Q input signals are sinusoids 90 degrees out of phase, then the output signal appears as a single sideband signal above or below the LO frequency. In this simulation, we sweep the amplitudes of the baseband input signals and we will look at distortion in the output spectrum as well as gain compression at various points in the transmit chain.

37



Simulation results

LO {1,0}

Output {1,1} LO toneindex

BB toneindex

Phase of Q input set 90 degrees behind phase of I inputRequired ~21 minutes for sweep

The spectrum shows the desired signal at the LO + baseband frequency. Undesired distortion terms are also present in the spectrum. The LO feedthrough would appear much larger if mismatch were included in the simulation, indicating a need for Monte Carlo analysis, since the amount of mismatch would be a random process. The gain compression plots show the amount of gain compression from the input to different points in the transmitter (blue is the output of the Q baseband chain, red is the output of the I baseband chain and is directly below the blue line, purple is the output of the mixer, and black is the output of the power amplifier.)The gain compression plots indicate that the mixer doesn’t contribute significantly to the overall gain compression until the baseband signal amplitude reaches about -37 dB. The amplifier contributes gain compression at a lower baseband input signal amplitude and is the main source of gain compression when the baseband input signal amplitude is above about -35 dB.

38



Double-sideband simulation resultsQ and I inputs in phase

Compression occurs earlier

This shows the results of the same simulation, except with the I- and Q-baseband input signals in phase, which produces a double-sideband output spectrum. A comparison with the previous plot indicates that gain compression occurs at a lower input signal amplitude. For example, the 1-dB gain compression input point has changed from about -36 dB to about -38 dB.In theory, you could extract an IP3 point from plots of the lower left-hand plot. However, the undesired distortion tone does not rise at a 3 dB/dB slope, because (from other simulations not shown here) the baseband filters do not exhibit a traditional third-order nonlinearity.What is the point of all this? Instead of attempting to characterize the distortion of the transmitter by just using sinusoids, how about using modulated baseband input signals? Then we could simulate the modulated in-band output power and characterize the distortion at various points in the chain via EVM.

39



With WLAN baseband input signalsScaleFact scales amplitude of I and Q baseband input signals

Required about 91 minutes

This shows simulation results with baseband WLAN I and Q input signals. These signals came from a Ptolemy simulation. The Ptolemy TimedDataWrite component will write .sig files, which the goldenGateLib USRIQPWS or USRIQVS sources are able to read directly. The amplitudes of the baseband sources have been swept by increasing a scale factor “ScaleFact” from 0.001 to 0.150. The spectral plots show the output spectra with the ScaleFact set to its lowest and highest values. The output power increases from 65 uW to 186 mW, or -11.9 dBm to 22.7 dBm.As an alternative, instead of sweeping the “ScaleFact” to vary the amplitude of the input signal, we could fix this amplitude and instead sweep the voltage that controls the gains of the baseband chains.

40



EVM at different points

PA Output

Mixer Outputs

BB Chain Outputs

This shows the EVM at different points in the transmitter, as a function of the scale factor. The biggest EVM occurs at the output of the PA, although the mixer does contribute some distortion.

41



Trajectory diagrams at power amplifier output

This shows the trajectory diagrams at the output of the power amplifier for the lowest and highest values of the scale factor. The right plot clearly shows compression relative to the left one.

42



Extracted view simulation with WLAN signalsScaleFact scales amplitude of I and Q baseband input signals

Extracted view simulation required about 8 hours

The previous two simulations were of schematic views. This simulation uses extracted views of the amplifier, mixers, and frequency divider. The output power with the scale factor at its highest value is now only 20.4 dBm. The EVM has gone down, but would likely increase if the PA were driven hard enough to reach the same output power as before.

43



Several additional capabilities

• Parallelism to speed up Monte Carlo (and other) simulations

• Job Manager

There are several capabilities GoldenGate offers that I wanted to emphasize. One is the use of multiple computers in parallel, that speeds up Monte Carlo and other simulations. This enables you to use relatively inexpensive computing power (even four CPUs within a single PC) to make these simulations something you would definitely include in your design flow, rather than skipping them entirely because they would be hopelessly time consuming.Another capability is the Job Manager, which is described on the next page.

44



Job Manager examples

Enables multiple simulations to be run from same ADE session

Harmonic “calibration”

Corner analysis

Various analyses in parallel (if multiple CPUs available)

The Job Manager enables you to run multiple simulations from the same ADE session. The simulations may be run sequentially on a single CPU or in parallel if multiple CPUs are available. Each simulation may have a different state associated with it. Corner analysis may be run by specifying that each state have a different model file definition. You may setup a series of harmonic balance simulations where the number of harmonics is varied to see how the results change. You may run a series of analyses (such as 1-tone, 2-tone, noise, and gain compression.) You could instead have these defined in a single artist state and not use Job Manager, but then the simulation would be run on a single CPU. Job Manager could be used in this case to run a corner analysis, with a sequence of simulations for each corner.

45



Additional examples from customers using GoldenGate• Harmonic Balance Capacity

– Receiver for Video Application 20K active devices, 20K passive– Noise figure analysis with SSNA (127 harmonics) < 12 hours

• Fast Envelope– 2800 Active devices, 3200 Passive elements, QAM 256 Source– ACPR produced with Fast Envelope in less than 3 minutes

• Verification + Parallel Processing– Full chain quad-band GSM, GPRS, GPS Tx/Rx– Running 70 simulations in parallel– Met spec on first tape out

• Ease of Use– RF MEMS crystal oscillator – 8hrs with simulator X -> 4 min with GoldenGate– Installed and purchase decision made in an afternoon

46



Conclusion

GoldenGate is “tuned” for easy block-level design and simulation

GoldenGate has the capacity to simulate large extracted viewsand multiple blocks together

GoldenGate’s Monte Carlo simulation capabilities (especiallywith parallelism) move statistical design from a step you skip tosomething you should do for every design

GoldenGate’s Fast Envelope Transient enables you to simulatereal system specifications

This summarizes the capabilities of GoldenGate.

www.agilent.com/fi nd/emailupdatesGet the latest information on the products and applications you select.

www.agilent.com/fi nd/agilentdirectQuickly choose and use your test equipment solutions with confi dence.

Agilent Email Updates

Agilent Direct

www.agilent.comFor more information on Agilent Technologies’ products, applications or services, please contact your local Agilent office. The complete list is available at:www.agilent.com/fi nd/contactus

AmericasCanada (877) 894-4414 Latin America 305 269 7500United States (800) 829-4444

Asia Pacifi cAustralia 1 800 629 485China 800 810 0189Hong Kong 800 938 693India 1 800 112 929Japan 0120 (421) 345Korea 080 769 0800Malaysia 1 800 888 848Singapore 1 800 375 8100Taiwan 0800 047 866Thailand 1 800 226 008

Europe & Middle EastAustria 0820 87 44 11Belgium 32 (0) 2 404 93 40 Denmark 45 70 13 15 15Finland 358 (0) 10 855 2100France 0825 010 700* *0.125 €/minuteGermany 01805 24 6333** **0.14 €/minuteIreland 1890 924 204Israel 972-3-9288-504/544Italy 39 02 92 60 8484Netherlands 31 (0) 20 547 2111Spain 34 (91) 631 3300Sweden 0200-88 22 55Switzerland 0800 80 53 53United Kingdom 44 (0) 118 9276201Other European Countries: www.agilent.com/fi nd/contactusRevised: March 27, 2008

Product specifi cations and descriptions in this document subject to change without notice.

© Agilent Technologies, Inc. 2008

For more information about Agilent EEsof EDA, visit:

www.agilent.com/fi nd/eesof

nstewart

Text Box

Printed in USA, July 24, 2007 5989-9995EN

presentation on characterization of a wlan...

Documents