advanced memory buffer (amb), characterization...

Advanced Memory Buffer (AMB),Characterization of Timing and VoltageSpecifications Application Note

Introduction

Higher CPU speeds drive theneed for higher memory band-width. For decades, CPUs haveconnected to the memory usinga parallel synchronous bus,running at speeds up to a cou-ple of hundred MHz. However,the speed of DDR2 technology,for example, limits the numberof DIMMs in a system becauseof the multi-drop routingnecessary. At the same time,other PC interfaces have suc-cessfully migrated to gigabitspeed, multiple-serial connecti-ons. These overcome the tech-nological problems at reasona-ble costs.

memory chips, and opens theway to using terabytes of RAM,with currently available DIMMs- as well as those already onthe road map.

As shown in figure 1, theinterface between the memorycontroller and the memory is apoint-to-point bus, with up to24 lanes. In the first generationof FBD solutions, this runs at3.2, 4.0 or 4.8 Gb/s. Thesespeeds may soon double. Theinterface consists of 10 south-bound lanes and12 to 14northbound lanes. The south-bound lanes transmit the com-mands from the CPU to thememory. The northbound lanestransport the data back to theCPU.

As each AMB chip buffers thesignal for its neighbours, thenorth and south ports areimplemented as TX and RX.Because each lane is differenti-al, an AMB chip can have upto 96 pins running at gigabitspeed[1].

Figure 1: FBD architecture

A new multiple serial interface,called Fully Buffered DIMM(FBD), applies this concept tomemory interfaces. It usesAdvanced Memory Buffer AMB)chips to connect the CPU tothe memory at gigabit speeds.

The AMB chip connects directlyto a DIMM using the currentparallel synchronous interface.The short tracks between thememory and the buffer help toeliminate common problemswith skew and signal integrity.This approach removes theimmediate need to redesign

Advanced Memeory Buffer

AMB chip specification

Figures 2 and 3 are taken fromthe AMB ReferenceSpecification[3] available at thetime of writing. The diagramsshow the eye specification, oreye mask, for the electricalsignals, for both input (RX)and output (TX). These applyto any lane, operating north-ward or southward.

The TX output is specifiedwith a programmable drivingstrength and de-emphasis. De-emphasis means the bit after atransition (a transitional bit) isdriven with higher amplitudethan a bit that has the samevalue as the preceding bit (ade-emphasized bit). De-empha-sis compensates for the degra-dation of frequency responseand losses in the channel,which in this case is the mot-herboard. This compensationreduces the jitter caused byInter-Symbol Interference (ISI)and provides better eye ope-nings of the transmitted signalsat the RX. This improves thejitter performance for thewhole channel. Apart fromcompensating for jitter, thisalso improves the power con-sumption.

The RX input is designed towork with a much smaller eyethan transmitted by the TX.This allows for amplitude lossin the channel and the defi-ciencies of the jitter compensa-tion.

In the time domain, the TXand RX signals are defined bya minimum eye openingTeye_min, where:Teye_min + total jitter = 1UIwhere UI is the unit interval.For the TX output, the mini-mum eye opening is 0.7 UI. Atthe RX input, it is 0.6 UI.

Figure 2: AMB TX Output Eye Specification

Figure 3: AMB RX Input Eye Specification

Voltage specifications are provi-ded for the differential signals.The TX output must be betweena minimum and maximumamplitude, taking the attenuati-on ratio of the de-emphasizedbit into consideration. The mini-mum amplitude for TX is 520mV. This corresponds to 350 mVwhen de-emphasized by 3.5 dB.The minimum input swing forRX is defined as 170 mV.


FBD/AMB test solution summary

Figure 4 shows the variety oftest solutions provided byAgilent Technologies for testingthe various layers of FBD andAMB functionality. Apart fromverification and characterizati-on, there are solutions forsystem level test and highvolume manufacturing test. This document focuses on cha-racterizing the timing and vol-tage parameters of the AMBchip, using the Agilent 81250ParBERT system, with the86100C Infiniium DCAj WideBandwidth Oscilloscope.Characterizing physical layerparameters means evaluatingthe electrical parameters of thehigh-speed inputs and outputsof the AMB chip, and compa-ring them with the refe-rences[3], [4].

Apart from the test equipmentdetailed below, testing the cha-racteristics needs a reliableconnection to the AMB chipunder test. For reliable signal measure-ments, properly designed trans-mission lines are important.These need controlled impedan-ces of 50 or 100 differen-tial, and minimized losses.Agilent provides three test fix-tures (see figure 3). Theseallow testing the bare chip(N4235A), of the AMB on aDIMM (N4236A), or of theAMB system channel (N4238A).

AMB chip fixturing

Figure 5: Test fixtures

Figure 4: Agilent’s test solutions for FBD / AMB

Agilent FB-DIMM Fixtures for Signal Quality Compliance

N4235A AMB PArametric TestN4236A DIMM PArametric Test N4238A SlotPArametric Probe


86100C Configuration

The 86100C DCAj is the mostprecise signal-integrity analysistool currently available. It hasthe lowest amplitude noisefloor, the lowest intrinsic jitter,the best jitter sensitivity and,with Option 200, it includesthe most accurate jitter analy-sis algorithms available[7].

To analyze differential electricalsignals, the best receiver modu-le is the 86117A with - a 50GHz bandwidth module.

The DCAj needs a clock signaltrigger. If a clock signal is notavailable on the device undertest, we use the 83496A-100clock recovery circuit with thestandard configuration. We canset this for any data rate bet-ween 50 Mb/s and 7.1 Gb/s (upto 13.5 Gb/s with Option 200).We can set the clock recoveryloop bandwidth at either 270KHz or 1.5 MHz (or from 15kHz to 10 MHz with Option300).

86100C DCAj system

• 86100C Mainframe with Option 001 and Option 200 (Option 201 is recommended,but not required).

• 86117A dual electrical recei-ver module (86112A provides a lower cost alternative butprovides 20 GHz band width only. Alternatively the 86118Aprovides up to 70 GHz bandwidth and with option HO1 askew adjust between the two channels.)

• 83496A-100 clock recovery module.

Figure 6: 86100C DCAj


Figure 7: 81250A ParBERT configuration

81250 ParBERT Configuration

The 81250A ParBERT systemoffers the highest flexibility forconfiguring multiple channelsto test multiple lanes or setupmultiple de-emphasis signals.For the first generation ofAMB, the 7 Gb/s modulesshould be sufficient. There isalways the possibility to upgra-de to 13.5 Gb/s.

The 7/13.5 Gb/s configurationcontains two clock groups:The first clock group containsthree 7/13.5 Gb/s PatternGenerators and one Analyzer.We need at least two genera-tors. The third generator canbe used, for example, for cros-stalk testing.The AMB chip needs a refe-rence clock at the frequency ofthe data rate divided by 24. Asthis is not binary, we need todo this with a second clockgroup equipped with a genera-tor module.

7/13.5 Gb/s ParBERT system• 1 x 81250A ParBERT with

#013 Firewire and #149 Frame

• 1 x E4875A User Software• 2 x E4809A 13.5 GHz Clock• 4 x N4872A/74A 13.5 G/7 G

Pattern Generator Module• 1 x N4873A/75A 13.5 G/7 G

Analyzer Module.

Additional equipment:• 33250 Arbitrary Waveform

Generator• 4 x power supplies• PC with USB connections and

Python Software installed• N4235A AMB Fixture


How to Setup the Equipment

For the test we need to setup:1. Clock: We configure theParBERT for two clock groups.The clock group with the singledata generator is the clocksource. We load this generatorwith an alternating pattern of12 '0's and 12 '1's. This pro-vides a reference clock withfrequency at a 24th of the datarate.

We connect the data output toSCK/SCKn of the fixture. Wealso connect the clock outputsto the external clock input ofthe other clock group, and tothe trigger input of the oscil-loscope.

AMB chips use spread spec-trum clocking (SSC), which wedo not deal with in this appli-cation note. For SSC testing wewould need an external signalgenerator (not in the equip-ment list) to provide the SSCmodulated clock to both clockgroups. For more details seereference [5].

2. We need to stimulate atleast two of the lowest threesouthbound lanes to the AMB.We use two generators drivingthe normal and inverted inputto force electrical idle with a 0V swing. We split the signalswith two power dividers tosupply them differentially toPS0 and PS1: This lets us drivetwo lanes with two generatorchannels.

3. For jitter tolerance testing,we split the output of 33250Awith a power splitter, and feedeach signal to the delay controlinput of the generators supply-ing PS0 and PS1.

4. We can connect the thirdgenerator differentially to anyother southbound lane. Thislets us measure the lane orcreate crosstalk.

5. We perform all analysis onthe differential signals. We con-nect the ParBERT analyzer tolane SS0 and the two inputs ofthe DCAj to SS1. We analyzethe differential signal by sub-tracting one signal from theother.

6. A PC with Python softwarecan read and write the regi-sters in the AMB over USBand the SMBus. The documen-tation of the E4235A fixtureprovides some basic informati-on on this.

Figure 8: Schematic of Test Setup

Figure 9: Equpiment Setup

7. We need to power the fixtu-re with 3.3 V, 1.8 V, 1.5 V and0.9 V. For this, we need tobuild a harness with bananajacks to plug into the fixture.


How to Set-Up the AMB Test

FrequencyAll the tests described here use 3.2Gb/s data rate, but the setup couldjust as easily be used at 4.8 Gb/s(9.6 Gb/s with 13 G)

Levels into southbound lanes:The basic levels are LOL = 0 V,HIL = 0.7 V. This gives a differen-tial level of 1.4 Vpp. The terminati-on voltage, Vt, is set to 0 V.For PS0 and PS1 set HIL to 1.4 V.

Set Analyzer:The termination is 0.55 V and thethreshold is 0.55 V if single ended,or 0 V if differential.

The test bits:Figure 10 shows the bit flow nee-ded. After electrical idle we needto go through TS0, TS1 and TS2before the AMB is in the rightmode to loop the incoming bits.Figure 11 shows the ParBERTsequence for stepping through thestates. There is one block for eachstate. Once started, the electricalidle is sent to the AMB. With theevent handling assigned to theCMD radio buttons, we can nowtransition from block to block.

Feedback:A Python script reads the AMBinternal status register (1,64h), thislets us verify the correct recogniti-on of each state[2]. With the DCAjconnected to SS1 we can monitorthe AMB output, and check thesignal when entering the trainingand all following states.

Figure 10: Training Sequences Details

Figure 11: Sequence for State Stepping


How to prepare forCharacterization

The difference between charac-terization and function test isthe need for an almost infinitelength pattern to and from theAMB to make the measure-ments. We adapt the ParBERTsequence, so after the initiali-zation with idle and the trai-ning sequences, it provides aPRBS pattern in an infiniteloop. We do not use the eventsany more: each training seg-ment loops long enough so theAMB recognizes it properly.Also, we now include theParBERT analyzer in thesequence. Block 5 providessynchronization to the PRBS

pattern; Block 6 does the BERmeasurement. We use thesequence shown in figure 12for all the following DCAj andBERT measurements.

We distinguish between twotypes of measurements: the TXand the RX tests. The TX testkeeps the input signal mostlythe same for all tests while theanalyzing tool moves within theoutput signal. For RX testing,we vary the voltage and timingparameters of the input signal,while watching the BER of theoutput signal. The BERchanging from 0 to 1e-9 is a

Figure 12: 81250A ParBERT Sequence for Waveform, BER, Timing and Jitter Test

good indicator of the point atwhich the input signal is for-ced to the limit of the inputcircuitry. We get themost accu-rate results by using the DCAjto calibrate the input signal.However, these measurementsare time-consuming, as theyneed much reconnecting


TX Results, WaveformMeasurements

We stimulate PS0/PS1 as des-cribed earlier with the verifica-tion sequence; then we look atSS0/SS1.The DCAj has many analysingcapabilities in Oscilloscope andEye/Mask mode to measureparameters such as the transi-tion time automatically.

The DCAj also provides a one-button jitter mode whichbreaks the jitter down intoextrapolated Tj, Rj, Dj(d-d),DDJ(p-p), DCD and ISI in acouple of seconds. Figure 13shows a screen shot of the jit-ter measurement on the SS1output.

As described earlier, the de-emphasis of the AMB outputsavoids or reduces ISI jitter byreducing output amplitude if abit is stable for two or morecycles, and driving transitionalbits with a higher amplitude.For de-emphasis the AMB out-puts can be set to 0 dB, 3.5dB, 6 dB or 9.5 dB. We use aPython script to write this intoAMB register 1,54h.

Figure 14: TX output signal for De-emphasis set to OdB, 3.5dB and 6dB (left to right)

Figure 13: Jitter Measurement with 86100C

We connect a 25 cm long back-plane providing 50Ω transmis-sion lines on FR4 material, dif-ferentially to the AMB output.This creates an ISI jitter of 22ps at the data rate and patternconfigured. We connect to theDCAj to the far end. From leftto right, figure 14 show theeyes with 0 dB, 3.5 dB and 6dB de-emphasis. The 3.5 dBsetting shows the most openeye.


TX Results, BER & TimingMeasurements

The 81250 ParBERT Analyzerhas a differential connection,which allows analysis of thetrue differential signal. Figure15 is the eye opening takenfrom the SS0 lane, with de-emphasis set to 3.5 dB.The classical BERT scan, whichis called Output TimingMeasurement in the ParBERT,sweeps the sampling point overtime and gives a graph withina couple of seconds. Apartfrom the graph, there is also atable giving numerical valuesfor Phase Margin, Rj, Dj andextrapolated Tj. Figure 16shows this BERT scan for thesame de-emphasis settings usedfor figure 14. Again, the de-emphasis of 3.5 dB providesthe most open eye and a mini-mum value for Dj. The time to perform a BERTscan depends heavily on howlow the BER shall be tested.The Tj at 1e-12 is always anextrapolation, as on the DCAj.For a BER less than 1e-12, themeasurement will last manyhours.

The Fast Total JitterMeasurement (FTM), shown infigure 17, uses a more efficientmethod. The FTM is the onlytool that measures BER downto 1e-12 in the fastest possibleway [8].

Figure 15: Differntial Eve Opening for De-emphasis 3.5db

Figure 16: Output Timimg Measurement for De-emphasis to ObB (top), 3.5dB (bottom)and 6dB (middle) at ISI backplane

Figure 17: Fast Total Jitter Measurement for De-emphasis 3.5dB


RX Results: Jitter Tolerance

The RX measurements work bychanging the input signal untilit causes stress to the AMBinput circuitry. We watch theBER of the AMB output signal.An increase in the BER signalsthat the input is no longerworking properly.

In the case of the jitter tole-rance measurement, we addsinusoidal jitter to the inputsignal. We do this by connec-ting the 33250A ArbitraryWaveform Generator to thedelay control input of theParBERT generator. We use apower splitter to provide thesinusoidal signal to both gene-rators supplying the data signalto the PS0 and PS1 lane.

The amplitude of the sinusoidalsignal defines the peak- to-peakdeviation of the data edge,which in turn defines thepeak- to-peak jitter. We increasethe amplitude of the sinusoidalsignal until the BER reading onthe ParBERT analyzer changesfrom 0 to less than 1e-9.The delay control input provi-des a typical conversion gainof 400 ps/V. We use this valueto convert the amplitude rea-ding into the applied jitter. Wealso need to consider that thepower splitter halves theamplitude.The more accurate but moretime-consuming method is toverify the input signal byreconnecting to the DCAj and

measuring the eye opening (asshown in figure 19).For a complete jitter tolerancemeasurement we need to repe-at this at various jitter fre-quencies. Finally, we put themeasured data in a spreads-heet, for visualization.

Figure 18 shows the results wegot from SS0. The figure provi-des two curves: one for thecase where we connect thegenerator directly to the AMBinput (without ISI), the otherwhen using the ISI backplanementioned earlier. What is mostnotable is that a relativelysmall amount of ISI reducesthe tolerance to sinusoidal jit-ter significantly.

Figure 18: Jitter Tolerance Test using sinusoidal jitter with and without ISI (22ps)


RX Results, Receiver minimumInput Eye

Here we first verify the specifi-cation for the minimum inputsignal. Then we figure out theabsolute minimum signal withwhich the device will work.From figure 3, the minimuminput signal is 170 mV swingat 0.6 UI. This specificationapplies to the pin of the AMB.

Before we start with the RXminimum input signal measure-ments on the AMB, we need tomeasure the signal degradationin the test jig. The N4235A testfixture is designed for veryclean impedance matching.However, we cannot neglect thelosses from the FR4 material.These losses degrade the signalamplitude. We need to determine thisdegradation and compensatethe voltage settings accordingly. To measure the degradation,the N4235A provides a 4 inchtest line. We stimulate thiswith a ParBERT generator andmeasure the signal with theDCAj. We compare the signalrunning through the test linewith the signal that bypassesit.As we will use transition timeconverters for signal conditio-ning later, we compare theamplitude degradation once forthe fast signal and once for theconverted signal. We found anamplitude loss of 15% for thefast signal, and 20% for theconverted signal. In both cases,we lose 5 ps eye opening whenrunning through the test line.We use these values to adjustfor the measurements that fol-low.

To create the signal accordingthe eye mask, we connect theParBERT generator via the 150ps transition time converter tothe DCAj input. On the DCAjwe create the mask accordingfigure 5 (initially, we ignorethe corrections needed for thedegradation caused by the fix-ture).The power dividers dividethe AMB input signal by a fac-tor of 4. The DCAj measuressingle ended, so the equivalentvoltage is 85 mV single ended,or 340 mV before the divider.We set the ParBERT generatorlevels to get a signal on theoscilloscope with 340 mVamplitude.

The BER reading must be 0.Theoretically, we should waitfor 1000 seconds with noerrors to verify the input willwork for BER less than 1e-12with a confidence level of95%[6].

Then we enable the delay con-trol and set the jitter modulati-on to get an eye opening of187 ps, as shown in figure 19.Now, before we connect to theAMB input, we need to adjustfor the signal degradation wemeasured. We increase theamplitude by 20% and reducethe jitter modulation by 5 ps.

Figure 19: Receiver min. Input Signal measured with 86100C DCAj, mask defined accor-ding [3], with 150ps converter


To verify the absolute minimumamplitude we remove the tran-sition time converters. With thejitter modulation turned off, wereduce the amplitude of thedata signal going to PS0/PS1by decreasing the HIL of thegenerators until the BER figureincreases from zero. We increa-se the HIL again by roughly 5mV so the BER reading is backto zero. Then we increase thesinusoidal jitter modulationuntil the BER shows the firstfailures. Again we decrease sothe BER is zero again.

Now we verify the input signalby connecting differentially tothe BERT analyzer, as shownin figure 20. As we measurethis before the power dividers,we need to divide the voltagereadings by 4 and adjust for15% degradation. We calculatedthe absolute minimum inputsignal at the AMB pin as 105mV at an eye opening of 68%.

Conclusions

Together, the ParBERT and theDCAj have proven to be effi-cient tools for verifying andcharacterizing the AMB chip.The N4235A is a reliable fixtu-re, with good performance foraccurate verification and mea-surement.

Figures 20: Receiver’s absolute minimum input Signal measured with ParBERT EyeOpening Measurement


References

[1] FB-DIMM Draft Specification:Architecture and Protocol, JEDECJESDxx-x Proposal, March 2005

[2] FB-DIMM Draft Specification:Advanced Memory Buffer (AMB) ,JEDEC JESDxx-x Proposal,October 2004

[3] FB-DIMM Draft Specification: HighSpeed Differential PTP Link at 1.5VJEDEC JC-16-04-xx Proposal,December 2004

[4] FB-DIMM Draft Specification: HighSpeed Differential PTP Link at 1.5V, Section 4JEDEC JC-16-04-xx Proposal,December 2004

[5] Next Generation I/O Bus, PCI-Express BER Test Solution,Agilent Product Note5989-2467EN

[6] Marcus Müller, Ransom Stephens,and Russ McHugh, "Total JitterMeasurement at Low ProbabilityLevels, Using optimised BERT ScanMethod - DesignCon 2005"; 5989-2933EN

[7] "Comparison of Different JitterAnalysis Techniques With a PrecisionJitter Transmitter", Agilent WhitePaper, Ransom Stephens and BrianFetz, et al., 5989-3205EN

[8] Fast total jitter Test SolutionAgilent Application Note5989-3151EN

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