modeling, design, ese370: circuit-level modeling, …ese370/fall2015/handouts/lec...penn ese 370...

1

ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems

Lec 25: November 6, 2015 Memory Overview

Penn ESE 370 Fall 2015 - Khanna

Midterm: Mean: 59

Std dev: 22

ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems

Lec 25: November 6, 2015 Memory Overview


Today

!  Memory "  Classification "  Architecture "  Memory core "  Periphery (time permitting)

!  Project 2 is on this

3 Penn ESE 370 Fall 2015 - Khanna

Semiconductor Memory Classification

RWM NVRWM ROM

EPROM

E2PROM

FLASH

RandomAccess

Non-RandomAccess

SRAM

DRAM

Mask-Programmed

Programmable (PROM)

FIFO

Shift Register

CAM

LIFO


Memory Architecture: Core

Word 0Word 1

Word 2

Word N-1

Word N-2

Input-Output

S0S1S2

SN-2SN_1

(M bits)

StorageCell

M bits

N W

ords

Word 0Word 1

Word 2

Word N-1

Word N-2

Input-Output(M bits)

StorageCell

M bits

Deco

der

A0

A1

AK-1

S0

N words => N select signalsToo many select signals

Decoder reduces # of select signalsK = log2N


Memory Architecture: Decoders

Word 0Word 1

Word 2

Word N-1

Word N-2

Input-Output

S0S1S2

SN-2SN_1

(M bits)

StorageCell

M bits

N W

ords

Word 0Word 1

Word 2

Word N-1

Word N-2


StorageCell

M bits

Deco

der

A0

A1

AK-1

S0

N words => N select signalsToo many select signals

Decoder reduces # of select signalsK = log2N


2

Array-Structured Memory Architecture


Row

Dec

oder

AK

AK+1

AL-1

2L-K

Column Decoder

Bit Line

Word Line

A0

AK-1

Storage Cell

Sense Amplifiers / Drivers

M.2K

Problem: ASPECT RATIO or HEIGHT >> WIDTH

Amplify swing torail-to-rail amplitude

Selects appropriateword


Latches/Register – Can Store a State

!  Build master-slave register from pair of latches !  Control with non-overlapping clocks


MOS NOR ROM

WL[0]

WL[1]

WL[2]

WL[3]

BL[0] BL[1] BL[2] BL[3]

GND

GND

VDD

Pull-up devices


MOS NOR ROM

WL[0]

WL[1]

WL[2]

WL[3]

BL[0] BL[1] BL[2] BL[3]

GND

GND

VDD

Pull-up devices

0 1 1 1


MOS NOR ROM

WL[0]

WL[1]

WL[2]

WL[3]

BL[0] BL[1] BL[2] BL[3]

GND

GND

VDD

Pull-up devices

0 1 1 1

1 1 0 0

0 1 0 1

1 1 1 1


MOS NAND ROM

WL[0]

WL[1]

WL[2]

WL[3]

BL[0] BL[1] BL[2] BL[3]

VDD

Pull-up devices

All word lines high by default with exception of selected row


3

MOS NAND ROM

WL[0]

WL[1]

WL[2]

WL[3]

BL[0] BL[1] BL[2] BL[3]

VDD

Pull-up devices


1 0 0 0


MOS NAND ROM

WL[0]

WL[1]

WL[2]

WL[3]

BL[0] BL[1] BL[2] BL[3]

VDD

Pull-up devices


0 0 1 1

1 0 1 0

0 0 0 0

1 0 0 0


Read-Write Memories (RAM)

• STATIC (SRAM)

• DYNAMIC (DRAM)

Data stored as long as supply is appliedLarge (6 transistors/cell)FastDifferential

Periodic refresh requiredSmall (1-3 transistors/cell)SlowerSingle Ended


Latches/Register – Can Store a State

!  Build master-slave register from pair of latches !  Control with non-overlapping clocks


Gate Based Latch

!  How many transistors in this latch?


6-transistor CMOS SRAM Cell

VDD

QQ

M1 M3

M4M2

M5

BL

WL

BL

M6


4


VDD

QQ

M1 M3

M4M2

M5

BL

WL

BL

M6



VDD

QQ

M1 M3

M4M2

M5

BL

WL

BL

M6

Assume 1 is stored (Q=1)

Assume bitlines

precharged to Vdd

Read Operation


CMOS SRAM Analysis (Read)

VDD

Q = 1Q = 0

M1

M4

M5

BL

WL

BL

M6

VDD VDDVDD

CbitCbit

kn M5,

2---------------

VDD2

------------ VTnVDD

2------------⎝ ⎠⎛ ⎞–⎝ ⎠

⎛ ⎞2

kn M1, VDD VTn–( )VDD

2------------

VDD2

8------------–⎝ ⎠

⎛ ⎞=

(W/L)n,M5 ≤ 10 (W/L)n,M1 (supercedes read constraint)

Assume 1 is stored (Q=1)


CMOS SRAM Analysis (Write)

VDD

Q = 1Q = 0

M1

M4

M5

BL = 1

WL

BL = 0

M6

VDD

kn M6, VDD VTn–( )VDD

2----------- VDD

2

8-----------–⎝ ⎠

⎛ ⎞ kp M4, VDD VTp–( )VDD

2----------- VDD

2

8-----------–⎝ ⎠

⎛ ⎞=

kn M5,

2-------------- VDD

2----------- VTn

VDD

2-----------⎝ ⎠⎛ ⎞–⎝ ⎠

⎛ ⎞2

kn M1, VDD VTn–( )V DD

2----------- VDD

2

8-----------–⎝ ⎠

⎛ ⎞= (W/L)n,M5 ≥ 10 (W/L)n,M1

(W/L)n,M6 ≥ 0.33 (W/L)p,M4

Assume 1 is stored

Write 0 to cell


Periphery

• Decoders

• Sense Amplifiers

• Input/Output Buffers

• Control / Timing Circuitry


4 input pass-transistor based column decoder

BL0 BL1 BL2 BL3

D

A0

A1

S0

S1

S2

S3 2 in

put N

OR

dec

oder

Advantage: speed (tpd does not add to overall memory access time)

Disadvantage: large transistor countonly 1 extra transistor in signal path


5

Sense Amplifiers

tpC ΔV⋅

Iav----------------=

make ΔV as smallas possible

smalllarge

Idea: Use Sense Amplifer

outputinput

s.a.smalltransition


Idea

!  Memory for compact state storage !  Share circuitry across many bits

"  Minimize area per bit # maximize density

!  Aggressively use: "  Pass transistors, Ratioing "  Precharge, Amplifiers

to keep area down


Admin

!  Homework 7 due Wednesday !  Midterm 2 solutions posted later today !  Today is withdraw date


modeling, design, ese370: circuit-level modeling, …ese370/fall2015/handouts/lec...penn ese 370...

Documents