TOPIC : Memory modeling

Topics to be covered :•How to model memory in Verilog•RAM modeling•Register Bank

How to model memory in Verilog

In digital simulation, one often needs to model register files, RAMs, and ROMs. Memories are modeled in Verilog simply as an array of registers.

Each element of the array is known as a word. Each word can be one or more bits. It is important to differentiate between n 1-bit registers and one n-bit register.

A particular word in memory is obtained by using the address as a memory array subscript.

Memories

Different types and sizes of memory, register file, stack, etc., can be formed by extending the vector concept. Thus the declerationReg [15:0] memory[511:0];

Declared an array called memory; it has 512 locations. Each location is 16 bits wide. The value of any chosen location can be assigned to a selected register or vice-versa; this constitutes memory reading or writing. The index used to refer a memory location can be a number or an algebraic expression which reduces to an integral value – positive, zero, or negative.

B = mem[3] //data stored at mem[3] is assigned to B

Memory

Reg mem1bit[0:1023]//Memory mem1bit 1k 1-bit words.

Reg [7:0] membyte[0:1023];//Memory membyte with 1k 8-bit words (bytes)

Membyte [511]//Fetches 1 byte word address is 511.

Memory decleration

Verilog provides a very useful system task to initialize memories from a data file. Two tasks are provided to read numbers in binary or hexadecimal format. Keywords $readmemb and $readmemh are used to initialize memories :

Usage: ◦ $readmemb(“<file_name>”, <memory_name>);◦ $readmemb(“<file_name>”,<memory_name>,<s

tart_addr>,<finish_addr>);◦ NOTE : <start_addr>,<finish_addr> are optional.

Initialization Memory from file

Initializing memory example

How do you model a RAM in Verilog

Basic Memory Model

SRAM - Simplified Read Operation

Solution 1

Solution 2

Basic DRAM Architecture

Fast Page Mode DRAM (FP DRAM)

A row is selected and the col. addresses are sequenced. A row is considered a page, consisting of multiple words.

Each word has a sep. col. address.

The sense amplifier buffers a page.

EDO DRAM (Extended Data Out DRAM)

-- Extra output latch between the sense ampl. and output buffer

-- allows overlap bet. Col. Select and previous data out

-- saves one cycle over FP DRAM

•FPM and EDO RAM controlled asynchronously by the processor or the memory controller.

•A synchronous DRAM interface will eliminate a small amount of time (thus latency) that is needed by the DRAM to detect the ras/cas and rd/wr signals. DRAM latches information to and from the controller on the active edge of the clock signal

•In addition to a lower latency I/O, after a proper page and column setup, an SDRAM may store the starting address internally and output new data on each active edge of the clock signal, as long as the requested data are consecutive memory locations. This is accomplished by adding a column address counter to the base DRAM architecture. This counter is seeded with a starting column address strobed in by the processor (or memory controller) and is thereafter incremented internally by the DRAM on each clock cycle.

SDRAM

Model of an SDRAM

Interface signals of SDRAMsignal name active I/O description

CLK clock N/A input system clock

nRST reset low input system reset

ADDR(20:0) memory address N/A input memory address for r/w access

WnR access type N/A input when low read transfer, when high write tran.

nAS address and data strobe low input starts transfer

nLBE(3:0) input mask for data low input input enable/disable for data

DIN(31:0) data input N/A input data to be written into sdram

A(10:0) address bus N/A output address or control signals into sdram

BS(1:0) bank select N/A output determines bank to which commands are executed

CKE clock enable high output sdram CKE input

DQM(3:0) data mask high outputsdram data masks, mask individual bytes during datawrite.

nCAS column address strobe low output sdram nCAS input

nCS chip select low output sdram chip select

nRAS row address strobe low output sdram nRAS input

nWE write enable low output sdram nWE input

nDTACK transmission acknowledge low outputacknowledges data transfer, strobe for data output from sdram

DATA_OUT_SDR data bus N/A output sdram data in bus

The write access

The read access

Register BankARMMIPS

Register Bank in ARM : Where?

multiply

data out register

instruction

decode

&

control

incrementer

registerbank

address register

barrelshifter

A[31:0]

D[31:0]

data in register

ALU

control

PC

PC

ALU bus

A bus

B bus

register

Register Bank of ARM : Detail

R0

R1

R2

R30

R31

5x32 Decoder

32x1MUX

32x1MUX

rs1

rs2

alu_in1

alu_in2

clk

write

32

32

5

5

5

32

rd

32

write_data

32 registers, each 32-bit wide. 30 are general purpose, R30(Hi) and R31(Low) are reserved for the results of long multiplication (64-bit result).

Register Bank of ARM : Number of registers

Register File

Write

RD2 RD3RD1

RA1 RA2 RA3

WD

Clk

Reset

WA

32 32 32

{Hi, Lo}

32

64

Read Address 1 Read Address 2 Read Address 3

Read Data 1 Read Data 2 Read Data 3

Write Data

Write Address5

555

Mul_64

64-bit Multiply Data

The register file has three read ports. Reading is done asynchronously and the addresses of the registers to be read are provided by RA1, RA2 and RA3 (each 5-bit wide) while the data of these addressed registers are reflected on RD1, RD2 and RD3 (each 32-bit wide).

Register Bank of ARM : Read Ports

Register File

Write

RD2 RD3RD1

RA1 RA2 RA3

WD

Clk

Reset

WA

32 32 32

{Hi, Lo}

32

64

Read Address 1 Read Address 2 Read Address 3

Read Data 1 Read Data 2 Read Data 3

Write Data

Write Address5

555

Mul_64

64-bit Multiply Data

Writing into the registers is done at the negative edge of a clock and is enabled by the write control signal. The address of the register to be written is supplied by WA (5-bit wide) and the data is provided by WD (32-bit wide).

Register Bank of ARM : Writing

Register File

Write

RD2 RD3RD1

RA1 RA2 RA3

WD

Clk

Reset

WA

32 32 32

{Hi, Lo}

32

64

Read Address 1 Read Address 2 Read Address 3

Read Data 1 Read Data 2 Read Data 3

Write Data

Write Address5

555

Mul_64

64-bit Multiply Data

MIPS data path : Register Bank

There are 32 32-bit registers in a MIPS datapath.

The register bank module includes ◦ two read register address inputs (5-bits each), ◦ one write register address input (5- bits), ◦ a write-enable signal input (1-bit), ◦ a write data input (32-bits), and ◦ two read data outputs (32-bits).

Register Bank : MIPS

On the positive edge of the write-enable input, the register bank will update the contents of the register at the write address with whatever data is on the write data bus.

The read data outputs are output asynchronously – i.e. they are a function of the read register addresses.

Register Bank : MIPS