penn ese370 fall 2014 -- townley & dehon ese370: circuit-level modeling, design, and...

Penn ESE370 Fall 2014 -- Townley & DeHon

ESE370:Circuit-Level

Modeling, Design, and Optimization for Digital Systems

Day 14: October 1, 2014

Layout and AreaMidterm 1 Average: 79.7 (of 85) Std. Dev.: 4.4

Problem 4 • Failure – my fault

– Should be: min(max(3*(Va-Vb),0),1)

• Failed to provide good diagnosis of restoration understanding– Noisy measurement

• Result– Exam not provide very high precision

assessment of students• Cannot distinguish A from B students


Exam Successes (not fail)

• Does provide enough information to diagnose anyone ein big trouble and should drop – separate the DF from AB

• Diagnose a few R C items– Need that down cold will use heavily

• Did focus you on understanding these items, including restoration


4

Today

• Layout– Transistors– Gates

• Design rules

• Standard cells


Layout


6

Transistor

Side view

Perspective view


7

Layout

• Sizing & positioning of transistors

• Designer controls W,L

• tox fixed for process– Sometimes

thick/thin oxide “flavors”


8

NMOS Geometry

Top view Perspective view

L

W


9

NMOS Geometry

Top view

L

W

• Color scheme– Red: gate– Green: source and drain

areas (n type diffusion)S DG


10

NMOS vs PMOS

Rabaey text, Fig 2.1Penn ESE370 Fall 2014 -- Townley & DeHon

• NMOS built on p substrate

• PMOS built on n substrate– Needs an N-well

11

PMOS Geometry

n well

L

W

• Color scheme– Red: gate– Orange: source and drain

areas (p type)– Green: n well

• NMOS built on p wafer– Must add n material to

build PMOS

S DG


12

Body Contact

• “Fourth terminal”• Needed to set

voltage around device– PMOS: Vb = Vdd

– NMOS: Vb = GND

• At right: PMOS (orange) with body contact (dark green)


13

Body Contact

• Needed to set voltage around device– PMOS: Vb = Vdd

– NMOS: Vb = GND

• What happens if NMOS body contact is Vdd?


14

Body Contact


– NMOS: Vb = GND

• What happens if NMOS body contact is Vdd?– Polarity of field wrong– Won’t invert channel


15

Body Contact


– NMOS: Vb = GND

• Always to same supply as the transistor might be connected in CMOS



Rotate All butPMOS Transistor90 degrees

17

Interconnect• Connect transistors

– Different layers of metal• “Contact” - metal to transistor• “Via” - metal to metal


18

Interconnect• Connect transistors

– Different layers of metal• “Contact” - metal to transistor• “Via” - metal to metal


19

Interconnect Cross Section

ITRS 2007Penn ESE370 Fall 2014 -- Townley & DeHon

20

Masks

• Define areas want to see in layer– Think of “stencil” for material deposition

• Use photoresist (PR) to form the “stencil”– Expose PR through mask– PR dissolves in exposed area– Material is deposited

• Only “sticks” in area w/ dissolved PR


21

Masking Process

• Goal: draw a shape on the substrate– Simplest example: draw a rectangle

Silicon wafer

Mask


22

Masking Process

• First: deposit photoresist

photoresist

Mask

Silicon wafer


23

Masking Process

• Expose through mask– UV light


24

Masking Process• Remove mask and

develop PR– Exposed area

dissolves– This is “positive

photoresist”


25

Masking Process• Deposit metal through PR

window– Then dissolve remaining PR

• Why not just use mask?– Masks are expensive– Shine light through mask to

etch PR– Can reuse mask


26

Reverse EngineerInverter Layout


27

Layout Revisited

• How to “decode” circuit from layout?


28



Power (Vdd)

GND

29


• Where is PMOS transistor?

• NMOS?


Power (Vdd)

GND

Penn ESE370 Fall2010 -- DeHon30

Layout to Circuit

• 1. Identify transistors


31

Inverter Layout

• Where is Input?


32

Inverter Layout

• Where is Output?


33

Layout to Circuit

• 2. Add wires


34

Layout to Circuit

• 2. Add wires

Penn ESE370 Fall 2010 -- Townley (DeHon)Penn ESE370 Fall 2014 -- Townley & DeHon

35

Inverter Layout

• What is structure at top and bottom?


36

Layout to Circuit

• 2. Add wires


37

Layout to Circuit

• 2. Add wires


38

Design Rules• Why not adjacent

transistors?– Plenty of empty

space– If area is money,

pack in as much as possible

• Recall: processing imprecise– Margin of error for

process variation


39

Design Rules• Contract between process engineer &

designer– Minimum width/spacing– Can be (often are) process specific

• Lambda rules: scalable design rules– In terms of = 0.5 Lmin (Ldrawn)– Can migrate designs from similar process– Limited scope: 22nm process != 1m


Design Rules: Some Examples


2

66

3

2

2

1.5

n doping

p doping

gate

contact

metal 1

metal 2

via

Legend

41

Layout #2 (practice)


42

Layout #2 (practice)

• How many transistors?– PMOS?– NMOS?

• How connected?– PMOS, NMOS?

• Inputs connected?• Outputs?• What is it?


43

Standard Cells• Lay out gates so that heights match

– Rows of adjacent cells– Standardized sizes

• Motivation: automated place and route– EDA tools convert HDL to layout



Standard Cell Area

inv nand3

All cellsuniformheight

Width ofchanneldeterminedby routing

Cell area

Identify the full custom and standard cell regions on 386DX diehttp://microscope.fsu.edu/chipshots/intel/386dxlarge.html

http://microscope.fsu.edu/chipshots/intel/386dxlarge.html

Standard Cell Layout Example


http://www.laytools.com/images/StandardCells.jpg

ALU in Standard Cell


http://www.erc.msstate.edu/mpl/distributions/scmos/images/alu_yongchen.gif


Standard Cell Area

inv nand3

All cellsuniformheight

Width ofchanneldeterminedby routing

Cell area

Identify the full custom and standard cell regions on 386DX diehttp://microscope.fsu.edu/chipshots/intel/386dxlarge.html

http://microscope.fsu.edu/chipshots/intel/386dxlarge.html

48

Big Idea

• Layouts are physical realization of circuit– Geometry tradeoff

• Can decrease spacing at the cost of yield• Design rules

• Can go from circuit to layout or layout to circuit by inspection


Admin

• HW5 out– Due Tuesday – (Thursday next week is Fall Break)

• Here on Friday


penn ese370 fall 2014 -- townley & dehon ese370: circuit-level modeling, design, and...

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