penn ese370 fall2010 -- dehon 1 ese370: circuit-level modeling, design, and optimization for digital...

Penn ESE370 Fall2010 -- DeHon1

ESE370:Circuit-Level

Modeling, Design, and Optimization for Digital Systems

Day 36: December 6, 2010

Transmission Lines

Last week + today

• General wire formulation• Lossless Transmission Line• Reflections at ends of line• See in action in lab• Where arise?• Termination• Implications• Discuss Lossy


Transmission Lines

• This is what wires/cables look like– Aren’t an ideal equipotential– Signals do take time to propagate– Shape and topology of wiring effects how

signals propagate • …and the noise effects they see


Transmission Lines

• Need to understand – How to model how to reason about– What can cause noise– How to engineer high performance

communication


Transmission Lines

• Cable: coaxial

• PCB– Strip line– Microstrip line

• Twisted Pair (Cat5)


Coaxial Cable• Inner core conductor: radius r• Insulator: out to radius R• Outer core shield (ground)

• RG-58 Z0= 50 – networking, lab

• (RG-59 Z0= 75 – video)


€

L =μ

2π

⎛

⎝ ⎜

⎞

⎠ ⎟lnR

r

⎛

⎝ ⎜

⎞

⎠ ⎟

€

Z0 =1

2π

⎛

⎝ ⎜

⎞

⎠ ⎟μ

ε

⎛

⎝ ⎜

⎞

⎠ ⎟lnR

r

⎛

⎝ ⎜

⎞

⎠ ⎟

Printed Circuit Board

• Stripline– Trace between planes


wt b

r

€

Z0 =1

4

⎛

⎝ ⎜

⎞

⎠ ⎟μ

ε

⎛

⎝ ⎜

⎞

⎠ ⎟ln

1+W btb +W b

⎛

⎝ ⎜ ⎜

⎞

⎠ ⎟ ⎟

Printed Circuit Board

• Microstrip line– Trace over single supply plane


wt

hr

0

€

Z0 =1

2π

⎛

⎝ ⎜

⎞

⎠ ⎟

μ

0.475ε r + 0.67( )ε 0

⎛

⎝ ⎜ ⎜

⎞

⎠ ⎟ ⎟ln

4h

0.536W + 0.67t

⎛

⎝ ⎜

⎞

⎠ ⎟

Twisted Pair

• Category 5 ethernet cable– 100– V=0.64c0


Termination / Mismatch

• Wires do look like these transmission lines

• We are terminating them in some way when we connect to gate– Need to be deliberate about how terminate,

if we care about high performance


Where Mismatch?

• Vias

• Wire corners?

• Connectors

• Board-to-cable

• Cable-to-cable


http://wiki.altium.com/display/ADOH/An+Overview+of+Electronic+Product+Development+in+Altium+Designer

http://www.fpga4fun.com/Hands-on_Flashy.html

Visualization

• http://www.williamson-labs.com/xmission.htm


End of Line Reflection


€

Vr =ViR − Z0

R + Z0

⎛

⎝ ⎜

⎞

⎠ ⎟

€

Vt =Vi2R

R + Z0

⎛

⎝ ⎜

⎞

⎠ ⎟

Termination Cases

• Parallel at Sink– Pix

• Series at Source– pix


Pipeline Bits

• For properly terminated transmission line– Do not need to wait for bits to arrive at sink– Can stick new bits onto wire


Limits to Bit Pipelining

• What limits?– Risetime/distortion– Clocking

• Skew• Jitter

– For bus• Wire length differences between lines


Eye Diagrams• Watch bits over line on scope

– Look at distortion– “open” eye clean place to sample

• Consistent timing of transitions• Well defined high/low voltage levels


http://en.wikipedia.org/wiki/File:On-off_keying_eye_diagram.svg http://focus.ti.com/analog/docs/gencontent.tsp?familyId=361&genContentId=41762&DCMP=ESD_Solutions&HQS=Other+OT+esd

Bad “eye”


http://archive.chipcenter.com/knowledge_centers/asic/todays_feature/showArticle.jhtml?articleID=12800254

Impedance Change

• What happens if there is an impedance change in the wire?


Z0=75, Z1=50

• At junction: – Reflects

• Vr=(50-75)/(50+75)Vi

– Transmits• Vt=(100/(50+75))Vi


€

ViR − Z0

R + Z0

⎛

⎝ ⎜

⎞

⎠ ⎟=Vr

€

Vi2R

R + Z0

⎛

⎝ ⎜

⎞

⎠ ⎟=Vt

Impedance Change Z0=75, Z1=50


What happens at branch?


Branch

• Transmission line sees two Z0 in parallel

– Looks like Z0/2


Z0=50, Z1=25

• At junction: – Reflects

• Vr=(25-50)/(25+50)Vi

– Transmits• Vt=(50/(25+50))Vi


€

ViR − Z0

R + Z0

⎛

⎝ ⎜

⎞

⎠ ⎟=Vr

€

Vi2R

R + Z0

⎛

⎝ ⎜

⎞

⎠ ⎟=Vt

End of Branch

• What happens at end?

• If ends in matched, parallel termination– No further reflections


Branch Simulation


Branch with Open Circuit?

• What happens if branch open circuit?


Branch with Open Circuit

• Reflects at end of open-circuit stub

• Reflection returns to branch– …and encounters branch again– Send transmission pulse to both

• Source and other branch

• Sink sees original pulse as multiple smaller pulses spread out over time


Open Branch Simulation


Bus

• Common to have many modules on a bus– E.g. PCI slots– DIM slots for memory

• High speed bus lines are trans. lines


Multi-drop Bus

• Ideal– Open circuit, no load


Multi-Drop Bus

• Capacitive load (stub) at drop?– If tight/regular enough, change Z of line


€

Z0 =L

C

Multi-Drop Bus

• Long wire stub?– Looks like branch

• may produce reflections


Lossy Transmission Line

• How do addition of R’s change?


Lossy Transmission Line

• R’s cause signal attenuation (loss)– Voltage, energy– Reduced signal swing at sink– Limits length of transmission line before

need to restore signal


Transmission Line Noise

• Frequency limits

• Imperfect termination

• Mismatched segments/junctions/vias/connectors

• Loss due to resistance in line– Limits length


Admin

• Proj3b due Friday


Idea

• Transmission lines – high-speed– high throughput– long-distance signaling

• Termination

• Signal quality


€

w =1

LC=

c0

ε rμ r

€

Z0 =L

C

€

Vr =ViR − Z0

R + Z0

⎛

⎝ ⎜

⎞

⎠ ⎟

penn ese370 fall2010 -- dehon 1 ese370: circuit-level modeling, design, and optimization for digital...

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