penn ese370 fall2012 -- dehon 1 ese370: circuit-level modeling, design, and optimization for digital...

Penn ESE370 Fall2012 -- DeHon1

ESE370:Circuit-Level

Modeling, Design, and Optimization for Digital Systems

Day 36: December 7, 2012

Transmission Line Scenarios

Repeaters in Wiring

Previously

• Transmission line (LC wire) reflection

• Unbuffered RC wire delay scales as L2

– 0.5 Rwire Cwire

– 0.5 L2 Ru Cu


Today

• Transmission Line Scenarios

• RC (on-chip) Interconnect Buffering


Transmission Line

• Data travels as waves

• Line has Impedance

• May reflect at end of line


€

ViR − Z0

R + Z0

⎛

⎝ ⎜

⎞

⎠ ⎟=Vr

€

Vi2R

R + Z0

⎛

⎝ ⎜

⎞

⎠ ⎟=Vt

€

w =1

LC=

c0

ε rμ r

€

Z0 =L

C

Impedance Change

• What happens if there is an impedance change in the wire? Z0=75, Z1=50– What reflections and transmission do we get?


Z0=75, Z1=50

• At junction: – Reflects

• Vr=(50-75)/(50+75)Vi

– Transmits• Vt=(100/(50+75))Vi


€

ViR − Z0

R + Z0

⎛

⎝ ⎜

⎞

⎠ ⎟=Vr

€

Vi2R

R + Z0

⎛

⎝ ⎜

⎞

⎠ ⎟=Vt

Impedance Change Z0=75, Z1=50


What happens at branch?


Branch

• Transmission line sees two Z0 in parallel

– Looks like Z0/2


Z0=50, Z1=25

• At junction: – Reflects

• Vr=(25-50)/(25+50)Vi

– Transmits• Vt=(50/(25+50))Vi


€

ViR − Z0

R + Z0

⎛

⎝ ⎜

⎞

⎠ ⎟=Vr

€

Vi2R

R + Z0

⎛

⎝ ⎜

⎞

⎠ ⎟=Vt

End of Branch

• What happens at end?

• If ends in matched, parallel termination– No further reflections


Branch Simulation


Branch with Open Circuit?

• What happens if branch open circuit?


Branch with Open Circuit

• Reflects at end of open-circuit stub

• Reflection returns to branch– …and encounters branch again– Send transmission pulse to both

• Source and other branch

• Sink sees original pulse as multiple smaller pulses spread out over time


Open Branch Simulation


Bus

• Common to have many modules on a bus– E.g. PCI slots– DIMM slots for memory

• High speed bus lines are trans. lines


http://en.wikipedia.org/wiki/File:DIMMs.jpg

Multi-drop Bus

• Ideal– Open circuit, no load


Multi-Drop Bus

• Impact of capacitive load (stub) at drop?– If tight/regular enough, change Z of line


€

Z0 =L

C

Multi-Drop Bus

• Long wire stub?– Looks like branch

• may produce reflections


Transmission Line Noise

• Frequency limits

• Imperfect termination

• Mismatched segments/junctions/vias/connectors

• Loss due to resistance in line– Limits length


Idea

• Transmission lines – high-speed– high throughput– long-distance signaling

• Termination

• Signal quality


€

w =1

LC=

c0

ε rμ r

€

Z0 =L

C

€

Vr =ViR − Z0

R + Z0

⎛

⎝ ⎜

⎞

⎠ ⎟

Back to RC Wire

(on-chip, no L)


Delay of Wire

• Long Wire: 1mm

• Rwire = 60K for the 1mm)

• Cwire = 0.16 pF for the 1mm)

• Driven by inverter– R0 = 25K

– C0 = 0.01 fF

– Assume velocity saturated, sized Wp=Wn=1

• Loaded by identical inverter


Formulate Delay

€

Rbuf × Cself +Cwire +Cload( ) + 0.5Rwire ×Cwire + Rwire ×Cload


Delay of inverter driving wire?

Should be able to do these calculations on final.

Calculate Delay

• Cload = 2 C0

• Rbuf = R0

• Cself = 2 C0 = 2 C0


€

Rbuf × Cself +Cwire +Cload( ) + 0.5Rwire ×Cwire + Rwire ×Cload

Buffer Middle

• Delay if add buffer to middle of wire?


Should be able to do these calculations on final.

Formulate and Calculate Delay


€

2 Rbuf × Cself +Cwire

2+Cload

⎛

⎝ ⎜

⎞

⎠ ⎟+ 0.5

Rwire2

×Cwire

2

⎛

⎝ ⎜

⎞

⎠ ⎟+Rwire

2×Cload

⎛

⎝ ⎜

⎞

⎠ ⎟

N Buffers

• Delay for N buffers?


€

N Rbuf × Cself +CwireN

+Cload ⎛

⎝ ⎜

⎞

⎠ ⎟+ 0.5

RwireN

×CwireN

⎛

⎝ ⎜

⎞

⎠ ⎟+RwireN

×Cload ⎛

⎝ ⎜

⎞

⎠ ⎟

€

N × Rbuf × Cself +Cload( ) + Rbuf ×Cwire + 0.5Rwire ×Cwire

N

⎛

⎝ ⎜

⎞

⎠ ⎟+ Rwire ×Cload

Minimize Delay

• How minimize delay?

• Differentiate &Solve for N:


€

N = 0.5Rwire ×Cwire

Rbuf × Cself +Cload( )

⎛

⎝

⎜ ⎜

⎞

⎠

⎟ ⎟

€

2 0.5Rwire ×Cwire × Rbuf × Cself +Cload( ) + Rbuf ×Cwire + Rwire ×Cload

€

N × Rbuf × Cself +Cload( ) + Rbuf ×Cwire + 0.5Rwire ×Cwire

N

⎛

⎝ ⎜

⎞

⎠ ⎟+ Rwire ×Cload

Equalizes delay in buffer and wire

Calculate: Delay at Optimum Stages for Example

• Rwire = 60K for the 1mm)

• Cwire = 0.16 pF for the 1mm)

• Rbuf=R0 = 25K

• Cself=Cload=2(C0 = 0.01 fF)=0.02fF


€


Segment Length

• Rwire = L×Runit

• Cwire = L×Cunit


€

N = 0.5Rwire ×Cwire


⎛

⎝

⎜ ⎜

⎞

⎠

⎟ ⎟

€

N = L 0.5Ru ×Cu


⎛

⎝

⎜ ⎜

⎞

⎠

⎟ ⎟

Optimal Segment Length

• Delay scales linearly with distance once optimally buffered


€

N = L 0.5Ru ×Cu


⎛

⎝

⎜ ⎜

⎞

⎠

⎟ ⎟

€

Lseg* =

L

N= 2


Ru ×Cu

⎛

⎝

⎜ ⎜

⎞

⎠

⎟ ⎟

Buffer Size?

• How big should buffer be?– Rbuf = R0/W

– Cload = 2 W C0 (assuming velocity saturation)

– Cself = 2 W C0


€


€

2 0.5Rwire ×Cwire ×R0

W× 1+γ( )2WC0 +

R0

W×Cwire + Rwire × 2WC0

Implication W

• Rwire = L×Runit

• Cwire = L×Cunit

W independent of Length– Depends on technology


€

W =R0 ×CwireRwire × 2C0

Delay at Optimum W

• With =1, 1+=2

• Same size as first term


€

2 0.5Rwire ×Cwire × R0 × 1+γ( )2C0 + 2 R0 ×Cwire × Rwire × 2C0

€

4 R0 ×Cwire × Rwire × 2C0

Ideas

• Wire delay linear once buffered

• Optimal buffering matches– Buffer delay– Delay on wire between buffers


Admin

• Final – Friday 12/14, noon, Moore 212

• Review – Wednesday, 12/12– Evening – time announced on piazza

• Andre out of town until Friday


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