instruction fetch & execute model – from intel’s perspective

Download INSTRUCTION FETCH & EXECUTE MODEL – FROM INTEL’S PERSPECTIVE

Post on 03-Oct-2015

219 views

Category:

Documents

3 download

Embed Size (px)

DESCRIPTION

CSC 5321: ADVANCED OPERATING SYSTEMS

TRANSCRIPT

  • CSC 5321: ADVANCED OPERATING SYSTEMS

    INSTRUCTION FETCH & EXECUTE MODEL

    FROM INTELS PERSPECTIVE

  • 1

    A program to be executed by a processor comprises of a list of instructions stored in memory. A computer is built to execute instructions that are written in a very simple type of language called machine language. Different types of computers have their own machine language, and can execute a program only if it is expressed in that language. So to execute programs written in other languages, they need to be first translated (compiled) into machine language. For example, the following C language statement Will be translated to following assembly language: The assembly instructions are in turn translated into machine instructions. When the CPU wants to execute a program it first stores (by reading it from storage device) that program (in machine language format, of course) in the computer's main memory (RAM or random access memory). Along with the program, memory can also hold data that is being used or processed by the program. Main memory consists of a sequence of locations. These locations are numbered, and the sequence number of a location is called its address. An address provides a way of picking out one particular piece of information from among the millions stored in memory. The CPU executes a program that is stored as a sequence of machine language instructions in main memory. It does this by repeatedly fetching an instruction from memory and then executing that instruction. This process of fetch an instruction, executes it, fetch another instruction, execute it, and so on forever -- is called the fetch-and-execute cycle. As shown in Figure 1, our example assembly code is translated into machine language and loaded into the main memory. The program counter (PC) will hold the address of the next instruction to be executed (we are assuming that each machine instruction is encoded in such a way that it takes 4 bytes each). So, as in Figure 1, when the first instruction is ready to be executed (fetched from memory location and decoded) in the instruction register (IR), the PC is pointing towards the next instruction (PC=PC+4) in-line to be executed. Let us now take a detailed overview of the fetch and execution cycle. To start off the fetch cycle, the address which is stored in the PC is transferred to the memory address register (MAR). The CPU then transfers the instruction located at the address stored in the MAR to the memory buffer register (MBR) via the data lines connecting the CPU to memory. This transfer from memory to CPU is coordinated by the control unit (CU). To finish the cycle, the newly fetched instruction is transferred to the IR and unless told otherwise, the CU increments (by size of instruction) the PC to point to the next address location in memory. All these require several clock cycle to finish. After the CPU has finished fetching an instruction, the CU checks the contents of the IR and determines which type of execution is to be carried out

    a = b +c; // Sum variable b & c and put the result into a

    load R3, b // Copy the value of b from memory to register R3 load R4, c // Copy the value of c from memory to register R4 add R3, R4 // Sum the contents of register R3 & R4 // Sum will be placed in register R3 store R3, a // Store the value of register R3 into memory cell a

  • 2

    Figure 1. The PC, IR and RAM next. This process is known as the decoding phase. The decoding phase performs different checks such as, whether the instruction is a privileged instruction, whether the processor have proper access to execute that instruction, is it a trap instruction etc. If the decoding phase finds any such anomalies, it will raise an exception. The CU will save the current PC value (so that after the exception is handled, the program could resume execution at the place after the exception raised instruction) and load the PC with the corresponding Interrupt Service Routines (ISR) start address and move to the kernel segment, so that the exception could be handled in the proper way. If everything is alright in the decoding phase then the instruction is now ready for the execution cycle. After the instruction is executed (the execution step is complex and detailed in its own context, which we are not describing for simplicity), the CU checks for any interrupts happened? If no interrupts are there to handle, then the next instruction will be fetched and the fetch and execution cycle continues again. On the other hand, if there is an interrupt to handle, then the CU will save the current PC value (so that after the interrupt is handled, the program could resume execution at the right place where it was suspended) and load the PC with the corresponding Interrupt Service Routines (ISR) start address and set the segment value to kernel segment, so that the interrupt could be handled in the proper way (interrupt must be handled in supervisor mode).

    Figure 2 shows the flowchart for the generic fetch and execute cycle and Figure 3 shows one for Intel Architecture. As Intel do not have any user/supervisor bit, the mode checking is complicated and we only show few important checks that the fetch & execute cycle performs. In case of a Trap instruction, there should be mechanisms by which the user program that performs the Trap could get the control back. Intel uses instruction RTE (Return from Exception) at the end of any Trap or exceptions, which recover the processs context and change to user segment.

    Fetch & Execute Logic

    3050

    load R3, b

    PC

    IR

    CPU

    load R3, b load R4, c add R3, R4 store R3, a

    1011111000101010..1

    1011111000110011..0

    1111101010101010..1

    1010110001010101..1

    3046

    3050

    3054

    3058

    RAM

    Memory Address

    Machine language

  • 3

    Figure 2: Generic Instruction Fetch & Execution Cycle

    Start

    Yes

    No

    IN HARDWARE IN HA

    RD

    WA

    RE

    Yes

    Yes

    No

    No

    Fetch an instruction from a memory address, found

    in the PC

    Load the instruction to IR

    Increment the PC, so that it will now point to the next

    instruction in memory

    Decode instruction in IR

    Any Interrupt ?

    Save current PC

    Load PC with a pre-determined value

    Set user/supervisor bit to 1

    Privileged ?

    U/S bit=1 ?

    Save current PC

    Load PC with a pre-determined value

    Set user/supervisor bit to 1

    Execute instruction in IR

  • 4

    Figure 3: Instruction Fetch & Execution Cycle in Intel Architecture

    Yes

    Yes

    No

    Yes No

    Yes

    No

    Yes No

    Yes

    IN HARDWARE

    No

    Start

    Fetch an instruction from a memory address, found in

    the PC

    Load the instruction to IR

    Increment the PC, so that it will now point to the next

    instruction in memory

    Decode instruction in IR

    Any Interrupt ?

    Save current PC

    Load PC with a pre-determined value

    Set current segment = kernel segment

    Execute instruction in IR

    PC Address > PAGE_OFFSET

    ?

    Is it in Kernel Segment?

    ?

    Destination= mode register

    ?

    Is it in Kernel Segment

    ?

    Its a TRAP

    ?

    No

    Privileged ?

    U/S bit =1 ?

    Set U/S bit to 1

  • 5

    Figure 4. A BIOS chip in the motherboard

    When the computer is powered up, the CU in the CPU will start the fetch and execute cycle and will continue to do so, until the computer is powered down. After the computer is turned on, the processor is suffering from amnesia; there is nothing at all in the memory (PC) to execute. Of course the hardware makers know this will happen, so they pre-program the processor to always look at the same place (physical address 0xfffffff0) in the system BIOS (Basic Input Output System) ROM (a read only, persistent memory chip, Figure 4) for the start of the POST (Power on Self Test) program. So, when the system is powered on, the PC is pre-loaded with that hardwired address. So the instruction on that location will be loaded into IR and the PC will be incremented and the fetch and execute cycle will continue. This way all the instructions listed afterwards in the BIOS will be executed by the processor. The instructions in BIOS normally do various tests to check that all essential hardware components are fine and initialize them, and will then start the operating system booting process. It will choose a boot device (floppy, CD, Hard disk, USB etc.) in the order listed in the BIOS. If no available boot device is found, it will print an error message and will halt. The BIOS instruction will read the first sector of the available boot device. The first sector of the boot device is called the boot sector. The boot sector contains a small program (boot loader, such as LILO or GRUB or Operating systems own boot loader) whose responsibility is to read the actual operating system from the disk and start it. So, when the boot loader is completely loaded into RAM, the last BIOS instruction will be a jump instruction, that will jump to the first instruction of the boot loader and puts that into the PC. So, execution is now transferred to the boot loader and the fetch and execute will now continue from the first instruction of the boot loader. Figure 5 shows this overall picture.

    Figure 5: Intel System Initialization

    RAM

    POST

    BIOS

    ROM

    CMOS

    Boot Prog.

    OS

    Loader Boot Device Power Up

    Hardware Process

    Data Flow

  • 6

    Afte

Recommended

View more >