computer architecture and the fetch-execute cycle memory addressing techniques memory addressing...

Computer Architecture and Computer Architecture and the Fetch-Execute Cyclethe Fetch-Execute Cycle

Memory Addressing TechniquesMemory Addressing Techniques

Learning ObjectivesLearning Objectives

Explain the concepts of direct, indirect, indexed, relative addressing and immediate addressing of memory when referring to low-level languages.

Memory Addressing TechniquesMemory Addressing Techniques

1.1. Direct AddressingDirect Addressing

2.2. Indirect AddressingIndirect Addressing

3.3. Indexed AddressingIndexed Addressing

4.4. Relative AddressingRelative Addressing

5.5. Immediate AddressingImmediate Addressing

1.1. Direct AddressingDirect Addressing

Direct AddressingDirect Addressing

Means that the value in the address part of a Means that the value in the address part of a machine code instruction is the address of the machine code instruction is the address of the data.data.Simple to use but does not allow access to all Simple to use but does not allow access to all memory addresses as there are memory memory addresses as there are memory addresses larger than can be held in the address addresses larger than can be held in the address part of an instruction.part of an instruction.

e.g. A 32-bit memory location may use 12 bits for the e.g. A 32-bit memory location may use 12 bits for the instruction code and 20 bits for the address of the data. instruction code and 20 bits for the address of the data.

This would allow for 2^12 (= 4096) instruction codes and 2^20 This would allow for 2^12 (= 4096) instruction codes and 2^20 (= 1 048 576) memory addresses.(= 1 048 576) memory addresses.However, a computer using 32-bit memory locations will have However, a computer using 32-bit memory locations will have 2^32 (= 4 294 967 296) memory addresses.2^32 (= 4 294 967 296) memory addresses.So direct addressing does not allow reference to all addresses So direct addressing does not allow reference to all addresses e.g. for a computer using 32-bit memory locations, addresses e.g. for a computer using 32-bit memory locations, addresses from 2^20 – 2^32 cannot be referred to.from 2^20 – 2^32 cannot be referred to.

Assembly Language Instructions

InstructionExplanation

Op Code Operand

LDD<address

>Load using direct addressing


LDD 117

Accumulator

Main memory

115 11011111

116 11011011

117 11001000

118 11011110

119 01011111

120 11011100

121 00011111

122 11000111

~ ~

200 11001111


LDD 117

Accumulator

11001000

Main memory

115 11011111

116 11011011

117 11001000

118 11011110

119 01011111

120 11011100

121 00011111

122 11000111

~ ~

200 11001111

2.2. Indirect AddressingIndirect Addressing

Indirect AddressingIndirect Addressing

Means that the value in the address part Means that the value in the address part of a machine code instruction is the of a machine code instruction is the address of the address of the data.address of the address of the data.

Why use indirect addressing?Why use indirect addressing?

Allows more memory to be accessed than Allows more memory to be accessed than direct addressing as the full size of register direct addressing as the full size of register is used for an address.is used for an address. If this value points to a location which holds If this value points to a location which holds

nothing but an address then 2^32 locations in nothing but an address then 2^32 locations in memory can be addressed.memory can be addressed.



Op Code Operand

LDD<address


LDI<address

>Load using indirect addressing


LDI 117

Accumulator

Main memory

115 11011111

116 11011011

117 11001000

118 11011110

119 01011111

120 11011100

121 00011111

122 11000111

~ ~

200 11001111


LDI 117

Accumulator

Main memory

115 11011111

116 11011011

117 11001000 = 200

118 11011110

119 01011111

120 11011100

121 00011111

122 11000111

~ ~

200 11001111


LDI 117

Accumulator11001111

Main memory

115 11011111

116 11011011

117 11001000 = 200

118 11011110

119 01011111

120 11011100

121 00011111

122 11000111

~ ~

200 11001111

3.3. Indexed AddressingIndexed Addressing

Indexed AddressingIndexed Addressing

IIndex ndex RRegister (egister (IRIR)) A special register which holds an integer A special register which holds an integer

value, which is added to the base address in value, which is added to the base address in the instruction currently in the CIR, to give a the instruction currently in the CIR, to give a new effective address of the data.new effective address of the data.

Indexed Addressing Indexed Addressing can be can be used once during used once during

oneone Fetch-Decode-Execute-Reset Cycle: Fetch-Decode-Execute-Reset Cycle:

To reach a particular To reach a particular element in an array or element in an array or field in a record.field in a record. IR = Offset of the IR = Offset of the

required element or required element or field from the start of field from the start of the array or record.the array or record.

Instruction address = Instruction address = Address of the start of Address of the start of the array or record.the array or record.

AddressAddress Data:Data:

100100 ……....

101101 ……....

102102 ……....

103103 ……....

104104 ……....

105105 ……....



Op Code Operand

LDD<address


LDI<address

>Load using indirect addressing

LDX<address

>Load using indexed addressing


LDX 117

Accumulator

Main memory

115 11011111

116 11011011

117 01110000

118 11011110

119 01011111

120 11011100

121 00011111

122 11000111

~ ~

200 11001111

Index Register

00000011


LDX 117

Accumulator

Main memory

Index Register

00000011 = 3

115 11011111

116 11011011

117 01110000

118 11011110

119 01011111

120 11011100

121 00011111

122 11000111

~ ~

200 11001111


LDX 117 + 3 = 120

Accumulator

Main memory

Index Register

00000011 = 3

115 11011111

116 11011011

117 01110000

118 11011110

119 01011111

120 11011100

121 00011111

122 11000111

~ ~

200 11001111


Accumulator

Main memory

Index Register

00000011 = 3

LDX 117 + 3 = 120115 11011111

116 11011011

117 01110000

118 11011110

119 01011111

120 11011100

121 00011111

122 11000111

~ ~

200 11001111


LDX 117 + 3 = 120

Accumulator

Main memory

Index Register

00000011 = 3

115 11011111

116 11011011

117 01110000

118 11011110

119 01011111

120 11011100

121 00011111

122 11000111

~ ~

200 11001111


LDX 117 + 3 = 120

Accumulator11011100

Main memory

Index Register

00000011 = 3

115 11011111

116 11011011

117 01110000

118 11011110

119 01011111

120 11011100

121 00011111

122 11000111

~ ~

200 11001111

Indexed AddressingIndexed Addressingcan be can be used repeatedlyused repeatedly

To allow a number of fields in contiguous records To allow a number of fields in contiguous records or contiguous elements in an array to be or contiguous elements in an array to be accessed by incrementing the Index Register (IR) accessed by incrementing the Index Register (IR) between each successive access instruction.between each successive access instruction.


Instr. ADD 100Instr. ADD 100

IR:IR: 44


100100 ……....

101101 ……....

102102 ……....

103103 ……....

104104 ……....

e.g. to add 5 memory locations

- 1



IR:IR: 33


100100 ……....

101101 ……....

102102 ……....

103103 ……....

104104 ……....



IR:IR: 22


100100 ……....

101101 ……....

102102 ……....

103103 ……....

104104 ……....



IR:IR: 11


100100 ……....

101101 ……....

102102 ……....

103103 ……....

104104 ……....



IR:IR: 00


100100 ……....

101101 ……....

102102 ……....

103103 ……....

104104 ……....

STOP

Why use Indexed Addressing?

Why not do something similar to the high-level instruction?

NewAddress = OriginalAddress + OffsetAdd NewAddress

Doing it this way would involve:Reserving two memory addresses:

Address & Offset.

8 Fetch-Decode-Execute-Reset cycles: Set the OriginalAddress, set the Offset, load the

OriginalAddress, add Offset, store the NewAddress, access the contents of this “indirect” NewAddress, load offset, check if offset is < or > than a specified condition (number of elements required) and either loop back or stop.


Indexed addressing avoids this: Note that it is usual to decrement instead of

incrementing as most computers have a command to test if a register is below 0, which provides a convenient method of stopping the loop.1. Set the IR = Number of elements required - 1

2. Access (Address of 1st element + IR)

3. Decrement IR by 1

4. Test if IR < 0 otherwise loop back to step 2. This only involves only 4 Fetch-Decode-Execute-

Reset cycles and one register (IR).Note the IR is in the processor, not memory so no memory locations are used in indexed addressing.


This means that the original access instruction as written in the code does not need to be modified .

Also avoids 4 additional cycles and using 2 memory locations.

Note the IR is in the processor, not memory so no memory locations are

used in indexed addressing.


Note for fields in a record then: Set the IR = (No of records required – 1)*offset Address in access instruction = Address of 1st record Decrement IR by offset.

For more research:

http://www.docstoc.com/docs/21677063/INSTRUCTION-ADDRESSING-MODES

4.4. Relative AddressingRelative Addressing

Relative AddressingRelative Addressing

Address in the instruction is the Address in the instruction is the displacementdisplacement from the from the current instruction’s address + 1 current instruction’s address + 1 (due to the PC being (due to the PC being incremented)incremented) already in the PC. already in the PC. Used mainly with jump instructions.Used mainly with jump instructions.

The address in the instruction The address in the instruction (via the MAR) (via the MAR) is added to the is added to the value in the PC.value in the PC.

e.g. e.g. The current instruction is in address 3000 and is The current instruction is in address 3000 and is Jump *45*Jump *45*, using , using relative addressing this means that the line wants to jump to an relative addressing this means that the line wants to jump to an instruction 45 lines ahead of the instruction 45 lines ahead of the nextnext instruction instruction (due to the PC being (due to the PC being automatically incremented by 1 during any Fetch-Decode-Execute-Reset Cycle this automatically incremented by 1 during any Fetch-Decode-Execute-Reset Cycle this means 46 lines ahead of the current instruction).means 46 lines ahead of the current instruction).

The PC will have been incremented to 3001 The PC will have been incremented to 3001 (ready for the next (ready for the next instruction)instruction) so the PC is changed to 3001+45 = 3046. so the PC is changed to 3001+45 = 3046. The next cycle retrieves the next instruction from there.The next cycle retrieves the next instruction from there.

The program knows where the line is relative to the current instruction but The program knows where the line is relative to the current instruction but not the true address – see not the true address – see Memory Management Presentation or next 2 Memory Management Presentation or next 2 slides.slides.

Therefore allows for relocatable code (code that be moved anywhere without Therefore allows for relocatable code (code that be moved anywhere without jump instructions etc… being affected).jump instructions etc… being affected).

Index TableIndex TablePhysical Page Physical Page

NumberNumberLogical Page Logical Page

NumberNumberBase Base

AddressAddress

88 55 30003000

Displacemente.g. 45

Physical Addresse.g. 3001+45 = 3046

+

Base AddressBase Address Segment SizeSegment Size SegmentSegment

35003500 15001500 33

Segment Index TableSegment Index Table

Displacemente.g. 131

Physical Addresse.g. 3501+131=3632

+

Relative AddressingRelative Addressing

Can also be used to access data Can also be used to access data in addresses relative to the in addresses relative to the current instruction.current instruction. The only difference is that the new “effective” address The only difference is that the new “effective” address

would be loaded into the MAR would be loaded into the MAR (contents of PC + operand (contents of PC + operand

of instruction in CIR) of instruction in CIR) and used from there, instead of the and used from there, instead of the going on to change the PC.going on to change the PC.

Relative Vs Indexed Addressing

Similar as they both involve changing an address by addition but:

Indexed Addressing:Changes the address in the instruction in the CIR.

Address limited to the size of the address field in the CIR, as in direct addressing.

Effective address = address in the CIR + contents of IR Relative Addressing:

Changes the address in the MAR and for Jump instructions the PC as well, not the address in the instruction in the CIR.

Address can be full value of the register as modified effective address is on its own in the PC or MAR.

Effective address = current instruction’s address + 1

+ value in instruction

For more researchFor more research

http://www.edsim51.com/8051Notes/http://www.edsim51.com/8051Notes/8051/instructionSetSummary.html8051/instructionSetSummary.html

http://en.wikipedia.org/wiki/http://en.wikipedia.org/wiki/Addressing_modesAddressing_modes

5.5. Immediate AddressingImmediate Addressing

Immediate Addressing

Immediate addressing is so-named because the value to Immediate addressing is so-named because the value to be stored in memory immediately follows the operation be stored in memory immediately follows the operation code in memory. code in memory.

e.g.e.g. “Load 20” where 20 refers to a value and is loaded directly “Load 20” where 20 refers to a value and is loaded directly into the accumulator.into the accumulator.

You could argue that there is no address being used at allYou could argue that there is no address being used at all, but , but there you go!there you go!

Immediate addressing is very fast since the value to be Immediate addressing is very fast since the value to be loaded is included in the instruction. loaded is included in the instruction. However, since the value to be loaded is fixed at However, since the value to be loaded is fixed at compile-time it is not very flexible.compile-time it is not very flexible.

Immediate Addressing

Advantage:Advantage: No memory reference other than instruction No memory reference other than instruction

fetch is required to obtain the data to be used. fetch is required to obtain the data to be used.

Disadvantage:Disadvantage: The size of the number is limited to the size of The size of the number is limited to the size of

the address field, which most instruction sets the address field, which most instruction sets is small compared to word length.is small compared to word length.

This is similar to the problem “direct addressing” This is similar to the problem “direct addressing” has.has.

For more research:

http://www.edsim51.com/8051Notes/8051/instructionSetSummary.html

http://www.docstoc.com/docs/21677063/INSTRUCTION-ADDRESSING-MODES

PlenaryPlenary

State the 5 methods of memory State the 5 methods of memory addressing and explain why they are used.addressing and explain why they are used.

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