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Page 1: Fetch Result Store Next Fundamental Concepts2014/06/16  · Reset Fetch instruction Decode Execute Instructions partitioned into three classes Branch Load/store Register-to-register
Page 2: Fetch Result Store Next Fundamental Concepts2014/06/16  · Reset Fetch instruction Decode Execute Instructions partitioned into three classes Branch Load/store Register-to-register

Fund

amen

tal C

once

pts

Proc

esso

r (CP

U):

the

activ

e pa

rt o

f the

com

pute

r, w

hich

doe

s all

the

wor

k (d

ata

man

ipul

atio

n an

d de

cisio

n-m

akin

g).

Data

path

: por

tion

of th

e pr

oces

sor w

hich

con

tain

s ha

rdw

are

nece

ssar

y to

per

form

all

oper

atio

ns

requ

ired

by th

e co

mpu

ter (

the

braw

n).

Cont

rol:

port

ion

of th

e pr

oces

sor (

also

in

hard

war

e) w

hich

tells

the

data

path

wha

t nee

ds to

be

don

e (t

he b

rain

).

Fund

amen

tal C

once

pts

(2)

Inst

ruct

ion

exec

utio

n cy

cle:

fetc

h, d

ecod

e,

exec

ute.

Fe

tch:

fetc

h ne

xt in

stru

ctio

n (u

sing

PC)

from

mem

ory

into

IR.

Deco

de: d

ecod

e th

e in

stru

ctio

n.

Exec

ute:

exe

cute

in

stru

ctio

n.

Inst

ruct

ion

Fetc

h

Inst

ruct

ion

Dec

ode

Ope

rand

Fe

tch

Exe

cute

Res

ult

Sto

re

Nex

t In

stru

ctio

n

Page 3: Fetch Result Store Next Fundamental Concepts2014/06/16  · Reset Fetch instruction Decode Execute Instructions partitioned into three classes Branch Load/store Register-to-register

Fund

amen

tal C

once

pts

(3)

Fetc

h: F

etch

nex

t ins

truc

tion

into

IR (I

nstr

uctio

n Re

gist

er).

Assu

me

each

wor

d is

4 by

tes a

nd e

ach

inst

ruct

ion

is st

ored

in a

wor

d, a

nd th

at th

e m

emor

y is

byte

ad

dres

sabl

e.

PC (P

rogr

am C

ount

er) c

onta

ins a

ddre

ss o

f nex

t in

stru

ctio

n.

IR

[[PC

]]

PC

[P

C] +

4

Sing

le B

us O

rgan

izatio

n

Dat

a lin

e

Add

ress

line

PC

MA

R

MD

R

Y

Inte

rnal

pr

oces

sor

bus

Mem

ory

bus

Z

MU

X

A

ALU

B

Con

stan

t 4

Sel

ect

Add

S

ub

XO

R

: A

LU

cont

rol

lines

C

arry

-in

IR

RO

R(n

1)

: :

TE

MP

Inst

ruct

ion

deco

der a

nd

cont

rol l

ogic

. . .

Con

trol s

igna

ls

Page 4: Fetch Result Store Next Fundamental Concepts2014/06/16  · Reset Fetch instruction Decode Execute Instructions partitioned into three classes Branch Load/store Register-to-register

Inst

ruct

ion

Exec

utio

n

An in

stru

ctio

n ca

n be

exe

cute

d by

per

form

ing

one

or m

ore

of th

e fo

llow

ing

oper

atio

ns in

som

e sp

ecifi

ed se

quen

ce:

Tran

sfer

a w

ord

of d

ata

from

one

regi

ster

to a

noth

er o

r to

the

ALU

(Arit

hmet

ic L

ogic

Uni

t).

Perf

orm

an

arith

met

ic o

r a lo

gic

oper

atio

n an

d st

ore

the

resu

lt in

a re

gist

er.

Fetc

h th

e co

nten

ts o

f a g

iven

mem

ory

loca

tion

and

load

them

into

a re

gist

er.

Stor

e a

wor

d of

dat

a fr

om a

regi

ster

into

a g

iven

m

emor

y lo

catio

n.

8

Rese

t

Initi

aliz

e M

achi

ne

Regi

ster

- to

-Reg

iste

r Br

anch

N

ot T

aken

Br

anch

Ta

ken

Inst

ruct

ion

Exec

utio

n Co

ntro

l Sta

te D

iagr

am (f

or e

ach

diag

ram

) Re

set

Fetc

h in

stru

ctio

n De

code

Ex

ecut

e In

stru

ctio

ns p

artit

ione

d

into

thre

e cl

asse

s Br

anch

Lo

ad/s

tore

Re

gist

er-to

-reg

ister

Di

ffere

nt s

eque

nce

thro

ugh

diag

ram

for

each

inst

ruct

ion

type

Co

ntro

ller m

anip

ulat

es th

e da

ta p

ath

to p

erfo

rm th

e in

stru

ctio

n

Init

Fetc

h In

str.

XEQ

In

str.

Load

/ St

ore

Bran

ch

Incr

. PC

Page 5: Fetch Result Store Next Fundamental Concepts2014/06/16  · Reset Fetch instruction Decode Execute Instructions partitioned into three classes Branch Load/store Register-to-register