chapter3. processor design. cpu function : to execute instructions stored in a memory. –...

Download Chapter3. Processor Design. CPU function : to execute instructions stored in a memory. – instruction cycle fetch cycle : fetch an instruction from main

Post on 04-Jan-2016

224 views

Category:

Documents

2 download

Embed Size (px)

TRANSCRIPT

  • Chapter3. Processor Design

  • CPU function : to execute instructions stored in a memory. instruction cycle fetch cycle : fetch an instruction from main memory execute cycle : decode the instruction, fetch any required operands, and perform the operation.

    The behavior of CPU : sequence of register transfer operations.

    CPU time( tCPU ) : the time required for the shortest CPU microoperation.

    Interrupt : I/O devices request service from CPU

    CPU Design issues 1. CPU should be as fast as the available technology permits. # of components in the CPU must be kept small. 2. Because of the size of the main memory, it must be constructed using less expensive and therefore slower technology than that of CPU.(1 to 10 ratio)

  • Von Noumann CPU design : the basic of almost all CPU design CPU operation form X1 := fi ( X1, X2 ) X1 and X2 denote CPU register( AC, DR or PC ) or an external memory location M(adr) fi : fixed-point addition/subtraction shifting and logical operation

    fetch operation IR.AR = M(PC) Two essential memory-addressing instruction load AC := M(adr) store M(adr) := AC

  • Architecture ExtensionsAdditional addressable registers can be provided for storing operands and addresses. (index registers or base registers) replacing the single accumulator by a set of registerThe capabilities of ALU can be extended from fixed-point addition/ subtraction to fixed-point multiplicationSpecial registers can be included to facilitate the transfer of control between instruction within a program (such as a flag register) The transfer of control between different subroutines due to interrupts or subroutine calls and returns is facilitated by special registers (such as PSW -Program status word- of IBM 360). Control is transferred by saving the current PSW in main memory and loading a new PSW into CPU. Control is returned to the first program by retrieving the previously saved PSW from memory and restoring to CPU. Most computers now use LIFO (last-in first-out) stack.Facilitate simultaneous processing of two or more distinct instructions by extending memory addressing circuits and adding sufficient buffer storage to CPU. ALU can be divided into K parts to execute K instructions at once : Pipelining

  • A coprocessor is a specialized instruction execution unit that can be coupled a microprocessor so that instructions to be executed by P can be included inprograms fetched by the microprocessor. For example, the floating-point instructions of Motorola 68020 can be executed bymeans of an auxiliary 68881 floating-point coprocessor.A set of coprocessor instructions are defined for the 68020 when 68020 fetchesand decodes such instructions, it transfer the command position to the coprocessor,which then execute it.

  • 3.2 Information representation A word : an information unit of fixed length ASCII code( 8bits ) American Standards Committee on Information Interchange fixed-point numbers b0b1bn-1 bi = {0,1}

    floating-point number

    M 2Emantissaexponent

  • To assign representation that identify the major information types Tag is used.

    Word format of Burroughs B 6500/7500

    Advantage : Instruction sets can be simplified and software errors can be detected

    Disadvantage : waste of memory

  • Error detection and correction parity bit : a single check bit The parity bit is appended to an n-bit word X = (x0, x1, , xn-1) to form ( n+1) bit word X* = (x0, x1, , xn-1, c0)

    even-parity : c0= x0 x1 xn-1 odd-parity : c0= 1 x0 x1 xn-1 If c0 = c0* ( the recomputed parity bit based on the received word ), then there is no single-bit error but maybe multiple even # of bits error.

  • Single-bit error correction for n-bit word.

    c: #of check bits required for single error correction. n+c : all possible single error locations

    2c n + c + 1 for n = 4 c 3 for n = 8 c 4 for n = 16 c 5

    These codes also have the ability to detect double errors SECDED ( Single Error Correction / Double Error Detection )

  • Example) 16 bit word X = ( x0, x1, , x15 ) 5 check bit ( c0, c1, c2, c3, c4 )

    (x0, x1, , x15, c0, c1, c2, c3, c4) (x0r, x1r, , x15r, c0r, c1r, c2r, c3r, c4r ) calculate a new set of check bits(c0*, c1*, c2*, c3*, c4*) from (x0r, x1r, , x15r)

    The error vector E=(c0r c0*, c1r c1*, c2r c2*, c3r c3*, c4r c4* ) If E = (0, 0, 0, 0, 0), then no detectable error has occurred.If E=(0, 0, 0, 1, 1), then a single fault in a bit common only to c3 & c4 is detected. The error caused to x0 to become x0 The error is corrected by changing x0r to x0r

    0123456789101112131415c0 =x2x5x10x11x12x13x14x15c1 =x4x5x6x7x8x9x10x15c2 =x1x2x3x7x8x9x14x15c3 =x0x2x3x5x6x9x12x13c4 =x0x1x3x4x6x8x11x13

  • Number Format 1. The types of numbers to be represented : integer, real number. 2. The range values 3. The precision of values 4. Hardware complexity Binary number - sign-magnitude

    + 5 : 0101 5 : 1101 Ones complement representation - positive number : same as sign-magnitude - negative number : bitwise logical complement + 5 : 0101 + 0 : 0 0 5 : 1010 0 : 1 1

  • Twos complement representation

    - positive number : same as sign-magnitude - negative number : do the bit-wise complement, then add 1 to the least significant bit, and ignore carry generated from the most significant bit

    5 : 0 1 0 1 1 0 1 0

    1 0 1 1

    - unique representation of 0

  • IEEE 754 standard 32 bit floating point number format

    M : a sign-magnitude binary numberThe magnitude part of a normalized sign-magnitude number has 1 as its mostsignificant digit. No need to store this 1.The complete mantissa, called significand, is actually 1.M The precision is effectively increased by 1 bit.The actual exponent value is computed as E-127.1 bit left(right) shift of Mcorresponds to incrementing( decrementing ) E by 1.

  • N = (1)S 2E127 ( 1.M ) for 0 < E < 255

    N = 1 0 1 1 1 1 1 1 1 0 0 0 = 2127127 ( 1.5 ) = 1.5 EMN = 0 0 1 1 1 1 1 1 0 0 0 = ( 1 )0 2127 127 (1.M ) = 11.75 0 0 1 1 1 1 1 1 1 1 1 0 0 0 EM

  • Magnitude range : 1 2126 ~ ( 2 223 ) 212732-bit fixed-point number range : 232 ~ 231 1

    If the result of a floating-point operation is not a valid floating-point number then a special code referred to as not-a-number( NaN ) is used.

    If E = 255 and M 0, then N = NaN If E = 255 and M = 0, then N = ( 1 )S If 0 < E < 255, then N = ( 1 )S 2 E 127( 1.M ) If E = 0 and M 0, then underflow If E = 0 and M = 0, then N = 0

  • Floating-point round-off error : caused by the fact that every number must be represented by a limited number of bits N1 + N2 = M1 2e1 + M2 2e2 For example, 1.1 23 + 1.01 22 = 22( 11 + 1.01 ) = 22 100.01 = 1.001 24

    1.10 01 23 + 1.010 01 22 = 23 ( 1.10 01 + 0.1010 01 )

    M1 = 1 0 0 1 M2 = 0 1 0 1 M2 21 = 0 0 1 0 0 123

  • Example of matrix multiplication: accumulation of roundoff errors : caused by the fact that every number must be represented by a limited number of bits A x B = C

    =

  • 3.2 Instruction sets - to specify an operation to be carried out and the set of operands or data to be used

    Basic Instruction Format

  • Addressing modes : How to specify the current value of data X - immediate addressing : when data X is constant, its value can be placed in the operand field - direct addressing : the corresponding operand field contains the address X of the storage location containing the required value - indirect addressing : the instruction contains the address W of a storage location which in turn contains the address X of the desired operand Intel 8085s MVI A, 99 immediate addressing MOV A, B direct addressing absolute addressing : require the complete operand address to appear in the instruction operand field relative addressing : the operand fields contain a relative address, and the effective address of an operand is some function

  • The reasons for relative addressing Since all the address information need not be included in the instruction, instruction

Recommended

View more >