332:437 lecture 17 fsm hardware modification for reliability

04/19/23 Bushnell: Digital Systems Design Lecture 17

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332:437 Lecture 17 FSM Hardware Modification for

Reliability

Material from An Engineering Approach to Digital Design, by William I. Fletcher, Englewood Cliffs, NJ: Prentice-Hall

Glitch elimination with holding registers Asynchronous inputs

Glitch suppression Modified design procedures Modified state assignment

Summary


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System Controller Architecture Refinement

1. Add input and output Holding Registers to eliminate glitches

Use separate SYNCH STROBE clock to synchronize asynchronous inputs – usually at higher frequency than system clock (2X or 4X)

Asynchronous input holding register• Use edge-triggered D flip-flops or SR

latches (need asynchronous set/reset inputs)


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Example of Unwanted Glitches


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State Machine Without Holding Registers


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State Machine with Input & Output Holding Registers


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State Machine with Holding & Async. Set/Reset Registers


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Need Glitch-Free State Change & Output Operation

Problem Finite State Machine transition111->000

Six possible transitions between 111 & 000


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Finite State Machine Transitions Figure shows many possible

transition paths in next state or output decoder outputs (which will be the next state or machine outputs)

Unavoidable problem with any decoder addressed with a sequence of non-unit Hamming distance inputs.


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Caused by Heisenberg Uncertainty Principle

Bank of FF’s triggered by same clock will not change state simultaneously

2nd Problem -- Nearly impossible to assign states to Finite State Machine so that state transitions are one Hamming distance apart (i.e., there is only a single bit change)


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Glitch-Suppression Methods

1. Fix output decoder Disable O/P decoder prior to state

change Maintain disabled condition for some

t after state change, to allow state change & transient to settle out

Main Problem: Outputs that must remain asserted through several clock cycles are not allowed


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Glitch–Suppression Methods (continued)

2. Use D-type Output Holding Register Eliminates glitches in outputs – allows

holding of outputs during multiple state changes


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Glitch-Free Timing with Output Holding Register


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Output Holding Register

Uses special OUTSTROBE pulse to clock Holding Register some phase delay after clock goes high


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Modified State Machine Design Procedure

1. Decide whether to minimize output decoder, # flip-flops, or next state decoder

If not minimizing #FF’s use Moebius counter or One-Hot Design

2. Design tight Flow Diagrams – lead to tight Mnemonic-Documented State Diagrams


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Modified State Machine Design Procedure (continued)

3. Use “minimal locus” & “reduced “input dependency” state assignment procedures


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State Assignment & Asynchronous Inputs

For reliable state changes follow this rule: Next states from a single state whose

branching is controlled by an asynchronous variable must be given unit distance state assignments. • Obviously applies to states that loop back

on themselves

Mark states controlled by asynchronous variables with *


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Two Corollaries

1. Branching conditions for a state must not be controlled by >1 asynchronous variable

2. Only 1 state variable should be affected by any state change


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Summary

Glitch elimination with holding registers Asynchronous inputs

Glitch suppression Modified design procedures Modified state assignment

332:437 lecture 17 fsm hardware modification for reliability

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