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FSM basics & optimization

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Sequential Logic OptimizationVineet Sahula

Finite State Machine- Model

p=2l

Input variables, xi Input vector I ={x ,x , ...x } j 1 2 l Input alphabet I={I ,I , ...I } 1 2 p

V. Sahula, 2012-13

Computer Arith. & Microarchitecture: FSM-1

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Finite State Machine- Model

q=2m Output variables, z i Input vector O ={z ,z , ...z } j 1 2 m Input alphabet O={O ,O , ...O } 1 2 q

V. Sahula, 2012-13

Computer Arith. & Microarchitecture: FSM-1

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Finite State Machine- Model

n=2k

State variables, yi Input vector S ={y ,y , ...y } j 1 2 k Input alphabet S={S ,S , ...S } 1 2 n

V. Sahula, 2012-13

Computer Arith. & Microarchitecture: FSM-1

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Machine Specification - Set theoritic

M=(I,O,S,): IS S

: IS O: S O

Mealy machineMoore machine

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Computer Arith. & Microarchitecture: FSM-1

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State Machine model -Tabularx S S1 S2 x X1 S2 S3 X2 S1 S2 S S1 S2 S3 X1 Y1 Y3 Y2 X2 Y2 Y1 Y3

S3

S2 X SS1 S2

S1X1 S2 Y1 S3 S2 S1

state

outputsX2

Y2

Y3S2 Y2 S1

Y1Y36

S3V. Sahula, 2012-13

Computer Arith. & Microarchitecture: FSM-1

Mealy Machine Model -GraphX2/Y2 X S S1 S2 S3 S2 X1 S1 X2 X1/Y1 S1 X2/Y1

Y1S3 Y3 S2 Y2 S1 S2

Y2X1/Y2 Y1 Y3 S3 X2/Y3

S2

X1/Y3

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Moore Machine Model -Graphx S S1 S2 S3 X2

X1S2 S3 S2

X2S1 S2 S1

YY2 Y1 Y3 S2/Y1 X2 X1 S1/Y2 X1

X1

S3/Y3

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Capabilities & Limitations of FSMs

What FSM can do?

Transit through sequence of states For input of a length of more than n vectors (each vector is l-tuple, and is one of p vectors)

Machine will arrive in one of n states for more than n inputs

Limitations

The FSM can transit to one of n-states The maximal length of non-repeating sequence is nComputer Arith. & Microarchitecture: FSM-1 9

V. Sahula, 2012-13

k-distinguishablility

Two states Si, Sj are distinguishable

If there exists at least one finite input sequence, which when applied to FSM M, causes different output sequence, depending on whether Si or Sj is INITIAL state The sequence which distinguishes these states is called a distinguishing sequence of pair (Si,Sj)

(Si,Sj) is called k-distinguishable, if a distinguishable seq. Of length k exists

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Computer Arith. & Microarchitecture: FSM-1

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k-equivalence

Two states Si, Sj are k-equivalent

If they are NOT k-distinguishable

If they are k-equivalent

They are also r-equivalent, r < k If they are k-equivalent for all k

They are equivalent

If states Si, Sj are equivalent

All their corresponding X-successors are also equivalentComputer Arith. & Microarchitecture: FSM-1 11

V. Sahula, 2012-13

State MinimizationGoal : identify and remove redundant states(states which can not be observed from the FSM I/O behavior)

Why : 1. Reduce number of latchesassign minimum-length encoding only as the logarithm of the number of states 2. Increase the number of unassigned states codes heuristic to improve state-assignment and logic-optimizationV. Sahula, 2012-13 Computer Arith. & Microarchitecture: FSM-1 12

Algorithmic State Minimization

Goal identify and combine states that have equivalent behavior Equivalent States:

Same output For all input combinations, states transition to same or equivalent states

Algorithm Sketch1. Place all states in one set 2. Initially partition set based on output behavior 3. Successively partition resulting subsets based on next state transitions 4. Repeat (3) until no further partitioning is required

states left in the same set are equivalent

Polynomial time procedureComputer Arith. & Microarchitecture: FSM-1

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State Minimization Definition

Completely-specified state machine two states are equivalent if outputs are identical for all input combinations Next states are equivalent for all input combinations equivalence of states is an equivalence relation which partitions the states into disjoint equivalence classes Incompletely specified state machines

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Computer Arith. & Microarchitecture: FSM-1

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Classical State Minimization1. Partition states based on input output values asserted in the state 2. Define the partitions so that all states in a partition transition into the same next-state partition (under corresponding inputs)

V. Sahula, 2012-13

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Classical State Minimization AlgorithmOnly for Completely specified Machines

1. Partition the set of internal states based on input output values asserted in the state 2. Define the partitions so that all states in a partition transition into the same next-state partition (under corresponding inputs)

V. Sahula, 2012-13

Computer Arith. & Microarchitecture: FSM-1

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Machine M1PS

NS x=0 x=1D,1D,0 B,1 B,0 F,1 C,0

(ABCDEF)(ACE)(BDF)

AB C D E F

E,0F,0 E,0 F,0 C,0 B,0

(ACE)(BD)(F)(AC)(E)(BD)(F) (AC)(E)(BD)(F)

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Example (FSM in PS-NS state format)Ex : 0A 1A 0B 1B 0C 1C 0D 1D 0E 1E 0F 1F 0G 1G 0H 1H B0 C0 D0 E0 F0 A0 H0 G0 B0 C0 D0 E0 F1 A0 H0 A0

G has other input-output response than other statesD has other input-output response than other states because it goes to G which is known to be non-equivalent stategoes to red and blue groups

(A,B,C,D,E,F,H) (G) (A,B,C,E,F,H)(G)(D) (A,C,E)(G)(D)(B,F)(H)

B and F go to D

Please check this using triangular table

States A, C and E can be combined to one state States B and F can be combined to one state

You can also marke each new group with a new symbol and check transitions to thus marked groupsComputer Arith. & Microarchitecture: FSM-1 18

V. Sahula, 2012-13

Example of partition based minimizationEx : 0A 1A 0B 1B 0C 1C 0D 1D 0E 1E 0F 1F 0G 1G 0H 1H B0 C0 D0 E0 F0 A0 H0 G0 B0 C0 D0 E0 F1 A0 H0 A0

(A,B,C,D,E,F,H)(G) (A,B,C,E,F,H)(G)(D) (A,C,E,H)(G)(D)(B,F) (A,C,E)(G)(D)(B,F)(H)

V. Sahula, 2012-13

Computer Arith. & Microarchitecture: FSM-1

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State Minimization Example

Sequence Detector for 010 or 110Input Sequence Reset 0 1 00 01 10 11 Next State Present State X=0 X=1 S0 S1 S2 S3 S4 S5 S6 S1 S3 S5 S0 S0 S0 S0 S2 S4 S6 S0 S0 S0 S0 Output X=0 X=1 0 0 0 0 1 0 1 0 0 0 0 0 0 0

0/0 0/0 S3 0/0 S1 1/0 S4 0/1

S0

1/0 0/0 S5 0/0 S2 1/0 S6 0/1 1/0

1/0

1/0

1/0

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Method of Successive PartitionsInput Sequence Reset 0 1 00 01 10 11 Next State Present State X=0 X=1 S0 S1 S2 S3 S4 S5 S6 S1 S3 S5 S0 S0 S0 S0 S2 S4 S6 S0 S0 S0 S0 Output X=0 X=1 0 0 0 0 1 0 1 0 0 0 0 0 0 0

( S0 S1 S2 S3 S4 S5 S6 ) ( S0 S1 S2 S3 S5 ) ( S4 S6 )

S1 is equivalent to S2 S3 is equivalent to S5 S4 is equivalent to S6

( S0 S3 S5 ) ( S1 S2 ) ( S4 S6 )( S0 ) ( S3 S5 ) ( S1 S2 ) ( S4 S6 )

V. Sahula, 2012-13

Computer Arith. & Microarchitecture: FSM-1

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Minimized FSM

State minimized sequence detector for 010 or 110Input Sequence Reset 0+1 X0 X1 Present State S0 S1' S3' S4' Next State X=0 X=1 S1' S3' S0 S0 S1' S4' S0 S0 Output X=0 X=1 0 0 0 1 0 0 0 0

S0 X/0 0/0 S3 X/0 0/1 S1 1/0 S4 1/0

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Computer Arith. & Microarchitecture: FSM-1

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Asynchronous sr flip-flopr

U2

Q

NOR2

U3s NOR2

notQ

U5s

U4

S

Q ~Q

U2QR

NAND2

SR_FFNAND2

r

U1

U3notQ

NAND2V. Sahula, 2012-13

NAND2Computer Arith. & Microarchitecture: FSM-1 23

asynchronous flip-flop sr

Q(t)Q(t+1) s 0 0 1 1 r 0 1 0 1 Q(t+1) 0 Q(t) 0 0 1 1 0 1 0

s 0 1 0

r 0 1

1-

1

-

0

V. Sahula, 2012-13

Computer Arith. & Microarchitecture: FSM-1

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Negated sr FF

not_s

U2Q

U5~S Q

NAND2

U3not_r NAND2 notQ

~R ~Q

SR_FF

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Negated sr FFThis version has negated inputs s r This FF realizes the function:s0 0 1 1

r0 1 0 1

Q(t+1)1 0 Q(t)

Q(t)Q(t+1)0 0 1 1 0 1 0 1

s0 1 0

r0 1 0 -

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Classical State Minimization AlgorithmInCompletely specified Machines

1. State transitions are NOT defined Pressure that machine starts only in KNOWN state, OR

Presume un-specified STATE to be labeled, may be T

2. Outputs are NOT defined

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Covering State

States Si, of M1 is said to cover or contain Sj of machine M2 iff every input sequence applicable to Sj is also applicable to SiAnd its application to M1 and M2 when they are initially in Si, Sj respectively, results in identical output sequences whenever th