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  • Synchronous Sequential Circuit Design

    55:032 - Introduction to Digital Design

  • MotivationAnalysis of a few simple circuits

    Generalizes to Synchronous Sequential Circuits (SSC)Outputs are Function of State (and Inputs)Next States are Functions of State and InputsUsed to implement circuits that control other circuits"Decision Making" logic

    Application of Sequential Logic Design TechniquesWord ProblemsMapping into formal representations of SSC behaviorCase Studies

    55:032 - Introduction to Digital Design

  • OverviewConcept of the Synchronous Sequential Circuits Partitioning into Datapath and ControlWhen Inputs are Sampled and Outputs AssertedBasic Design ApproachSix Step Design ProcessAlternative SSC RepresentationsState Diagram, VHDLMoore and Mealy MachinesDefinitions, Implementation ExamplesWord ProblemsCase Studies

    55:032 - Introduction to Digital Design

  • Concept of the Synchronous Sequential Circuit Complex Digital System = Datapath + ControlRegistersCombinational Functional Units (e.g., ALU)BussesSSC generating sequences of control signalsInstructs datapath what to do nextThe workerThe SupervisorStatusControlControlDatapathStateControlOutputsStatusInputs

    55:032 - Introduction to Digital Design

  • Concept of the Synchronous Sequential CircuitExample: Odd Parity CheckerAssert output whenever input bit stream has odd # of 1'sStateDiagramSymbolic State Transition TableEncoded State Transition TableEven [0]Odd [1]Reset0011

    55:032 - Introduction to Digital Design

  • Concept of the Synchronous Sequential CircuitExample: Odd Parity CheckerNext State/Output FunctionsNS = PS xor PI; OUT = PSD FF ImplementationT FF ImplementationTiming Behavior: Input 1 0 0 1 1 0 1 0 1 1 1 0DRQQInputCLKPS/Output\ResetNSTRQQInputCLKOutput\Reset

    55:032 - Introduction to Digital Design

  • Concept of the Synchronous Sequential CircuitTiming: When are inputs sampled, next state computed, outputs asserted?State Time: Time between clocking eventsClocking event causes state/outputs to transition, based on inputsFor set-up/hold time considerations:Inputs should be stable before clocking eventAfter propagation delay, Next State entered, Outputs are stableNOTE: Asynchronous output (Mealy) take effect immediatelySynchronous outputs (Moore) take effect at the next clocking eventE.g., tri-state enable: effective immediatelysync. counter clear: effective at next clock event

    55:032 - Introduction to Digital Design

  • Concept of the Synchronous Sequential CircuitOn rising edge, inputs sampled; outputs, next state computedAfter propagation delay, outputs and next state are stableImmediate Outputs:affect datapath immediatelycould cause inputs from datapath to changeDelayed Outputs:take effect on next clock edgepropagation delays must exceed hold timesExample: Positive Edge Triggered Synchronous System

    55:032 - Introduction to Digital Design

  • Concept of the Synchronous Sequential CircuitCommunicating State MachinesMachines advance in lock stepInitial inputs/outputs: X = 0, Y = 0One machine's output is another machine's input

    55:032 - Introduction to Digital Design

  • Sequential Circuit AnalysisStart with schematic diagramNeed to determine how circuit worksTrace schematic, determine equations of operationFF input equationssequential circuit output equationsCreate State transition tableSequential circuit inputs, FFs are comb. logic inputsOrganize truth table as current state (FFs) and inputsCreate FF input, seq. Circuit output columnsFrom FF char. Tables, determine FF next state values

    55:032 - Introduction to Digital Design

  • Sequential Circuit Analysis (cont.)Generate State DiagramCircles (nodes) represent current or present state valuesLines (arcs) represent how state and output values changeGiven the current state and current inputs, the next state and output values are indicated by the associated arcState diagram can have different forms depending on the type of sequential circuit output.PresentStateValueNextStateValueInputs/outputs

    55:032 - Introduction to Digital Design

  • Basic Design ApproachSix Step Process

    1. Understand the statement of the Specification2. Obtain an abstract specification of the SSC3. Generate State Table4. Perform state assignment5. Choose FF types to implement SSC state register6. Implement the SSC

    55:032 - Introduction to Digital Design

  • Basic Design ApproachExample: Vending Machine SSCGeneral Machine Concept:deliver package of gum after 15 cents deposited

    single coin slot for dimes, nickels

    no changeBlock DiagramStep 1. Understand the problem:Draw a picture!

    55:032 - Introduction to Digital Design

  • Vending Machine ExampleTabulate typical input sequences:three nickelsnickel, dimedime, nickeltwo dimestwo nickels, dimeDraw state diagram:Inputs: N, D, reset

    Output: openStep 2. Map into more suitable abstract representation

    55:032 - Introduction to Digital Design

  • Vending Machine ExampleStep 3: State Minimizationreuse stateswheneverpossibleSymbolic State Table

    55:032 - Introduction to Digital Design

  • Vending Machine ExampleStep 4: State EncodingState

    0

    5

    10

    15NOTE!For D-FFs the next state will be what is at the D input. So each FFs next state values in the state table must be the D inputs for that FF.D1 D0

    55:032 - Introduction to Digital Design

  • Vending Machine ExampleStep 5. Choose FFs for implementationD FF easiest to use8 Gates

    55:032 - Introduction to Digital Design

  • Designing with SR, JK, and T Flip-FlopsSequential design with D-FFs is easy; next state depends on D input onlyWe can use other FFs but the process is a little more involvedState table defines set of present state to next state transitionsWhat we need to design the next state combinational logic is the FF input values needed for each Q Q+ transitionThis table is known as the FF excitation tableDerived from the FF characteristic table

    55:032 - Introduction to Digital Design

  • Derivation of JK Excitation TableJK Characteristic TableJK Excitation TableJ

    00001111K

    00110011Q

    01010101Q+

    01001110Q+

    0101Q

    0011J

    01XXK

    XX10

    55:032 - Introduction to Digital Design

  • Flip-Flop Excitation TablesQ+

    0101Q

    0011J

    01XXK

    XX10S

    010XR

    X010T

    0110D

    0101You can use any FF type for your implementation

    FF types can be mixed; I.e. in vending machingeyou could use a JK FF for Q1 and a T FF for Q0

    55:032 - Introduction to Digital Design

  • Vending Machine ExampleStep 5. Choosing FF for ImplementationJ-K FFRemapped encoded state transition table using JK excitation tableInputs JK Excitation TableQ+

    0101Q

    0011J

    01XXK

    XX10

    55:032 - Introduction to Digital Design

  • Vending Machine ExampleJ1 = D + Q0 N

    K1 = 0

    J0 = N + Q1 D

    K0 = Q1 N7 GatesImplementation:

    55:032 - Introduction to Digital Design

  • Moore vs. Mealy MachinesDefinitionsMoore Machine

    Outputs are functionsolely of the current state

    Outputs change synchronously withstate changesMealy Machine

    Outputs depend onstate AND inputs

    Input change causesan immediate (asynchronous) output changeState RegisterClockStateFeedback XInputs ZOutputsCombinationalLogic forNext State(FF Inputs)Comb.Logic forOutputs)Mealy only; no connection for Moore

    55:032 - Introduction to Digital Design

  • Moore and Mealy MachinesState Diagram EquivalentsOutputs are associated with StateOutputs are associated with TransitionsReset/0N/0N/0N+D/1150510D/0D/1(N D + Reset)/0Reset/0Reset/1N D/0N D/0MooreMachineResetNNN+D[1]150510[0][0][0]N D + ResetResetResetMealyMachineD

    55:032 - Introduction to Digital Design

  • Moore and Mealy MachinesStates vs. TransitionsMealy Machine typically has fewer states than Moore Machine for same output sequenceSame I/O behavior

    Different # of states1101200[0][0][1]1/0010/00/01/110

    55:032 - Introduction to Digital Design

  • Moore and Mealy MachinesSynchronous Mealy MachineLatched state AND outputsAvoids glitchy outputs!Outputs are delayed by up to 1 clock periodUsually equivalent to the Moore formState RegisterClockStateFeedback XInputs ZOutputsCombinationalLogic forNext State(FF Inputs)Comb.Logic forOutputs)Output RegisterClock

    55:032 - Introduction to Digital Design

  • Synchronous Sequential Circuit Word ProblemsMapping English Language Description to Formal SpecificationsFour Case Studies:

    Finite String Pattern Recognizer

    Complex Counter with Decision Making

    Traffic Light Controller

    Digital Combination Lock

    55:032 - Introduction to Digital Design

  • Synchronous Sequential Circuit Word ProblemsFinite String Pattern RecognizerA finite string recognizer has one input (X) and one output (Z).The output is asserted whenever the input sequence 010has been observed, as long as the sequence 100 has never beenseen.

    Step 1. Understanding the problem statement

    Sample input/output behavior:X: 00101010010Z: 00010101000

    X: 11011010010Z: 00000001000

    55:032 - Introduction to Digital Design

  • Synchronous Sequential Circuit Word ProblemsFinite String RecognizerStep 2. Draw State Diagrams for the strings that must be recognized. I.e., 010 and 100.Moore State DiagramReset signal places SSC in S0Outputs 1Loops in StateReset1000010,1S1/0S0/0S2/0S3/1S4/0S5/0S6/0

    55:032 - Introduction to Digital Design

  • Synchronous Sequential Circuit Word Pro