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implementation of car parking lot using FSM on fpga using verilog HDL

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IMPLEMENTATION OF CAR PARKING LOT USING FSM MODELLING ON FPGAByN.SAI MANI BHARATHM.Tech 1st YEAREMBEDDED SYSTEMSABSTRACT

Car parking system is implemented using Finite State Machine Modelling. The system has two main modules i.e1)Identification module and 2) slot checking module. Identification module identifies the visitor. Slot checking module checks the slot status. These modules are Modelled in HDL and implemented on FPGA. A prototype of parking system is designed with various interfaces like sensor interfacing, stepper motor and LCD. FSM:State machines or FSM are the heart of any digital designController of any processor is about a group of state machines.

There are two types of state machines as classified by the types of outputs generated from eachMELAY FSMMOORE FSMMELAY FSM:Mealy State Machine where one or more of the outputs are a function of the present state and one or more of the inputs. More sensitive to the changes in the inputs Reqiures less no states compared to Moore state machine.MOORE FSM:Moore State Machine where the outputs are only a function of the present state Less sensitivity to changes in inputs Requires more no states.INTRODUCTION

FSM using VerilogFSM code should have three sections:Encoding Style .Combinational Part (Next State Logic and output Logic).Sequential Part (State Registers).FSM Using Verilog Encoding Style: Binary Encoding: parameter [1:0] S0 = 2b00; parameter [1:0] S1 = 2b01; parameter [1:0] S2 = 2b10; parameter [1:0] S3 = 2b11;One hot Encoding: parameter [3:0] S0 = 4b0001; parameter [3:0] S1 = 4b0010; parameter [3:0] S2 = 4b0100; parameter [3:0] S3 = 4b1000;Gray Encoding (Only 1-bit should change from previous value): parameter [2:0] S0 = 3b000; parameter [2:0] S1 = 3b001; parameter [2:0] S2 = 3b011; parameter [2:0] S3 = 3b010;REQUIREMENTS:

Xilinx ISEFPGA BOARDLCD DISPLAYMOTORIR SENSOR MODULES POWER SUPPLY

FPGALCDULN 2003STEPPER MOTORBLOCK DIAGRAMPOWER SUPPLYIR SENSOR MODULE AIR SENSOR MODULE BXilinx ISE contains all the aspects required for Devolopment flowVarious tools provided by Xilinx are Xilinx Project Navigator Xilinx synthesis tool-XST Xilinx Simulation ToolImpactModelSimXilinx ISE Project Navigator is a graphical interface for users to access software tools and relevant files associated with a project. It consists of four windows Source window Process window Transcript window Workplace windowXilinx project Navigator

PROCESS INVOLVED DURING ENTRANCEIR SENSOR RX AIR SENSOR TX AIR SENSOR TX BIR SENSOR RX B

A=0&B=0A=1&B=0

\A=1&B=1A=0&B=1IR SENSOR TX AIR SENSOR TX BIR SENSOR RX BIR SENSOR RX AIR SENSOR TX BIR SENSOR TX AIR SENSOR RX B

IR SENSOR RX AIR SENSOR TX BIR SENSOR RX BIR SENSOR TX AIR SENSOR RX APROCESS INVOLVED DURING EXITIR SENSOR RX AIR SENSOR TX AIR SENSOR TX BIR SENSOR RX B

A=0&B=0A=0&B=1

\A=1&B=1A=1&B=0IR SENSOR TX AIR SENSOR TX BIR SENSOR RX BIR SENSOR RX AIR SENSOR TX BIR SENSOR TX AIR SENSOR RX B

IR SENSOR RX AIR SENSOR TX BIR SENSOR RX BIR SENSOR TX AIR SENSOR RX AS1A=1B=0

S5A=0 B=1S2A=1B=1S3A=0B=1S6A=1B=1S7A=1B=0S4ENTER/1S8EXIT/1S0A,B=0STATE DIAGRAMThere are four major steps involved :Create the design project and HDL codes. Create a Testbench and perform RTL simulation. Add a constraint file and synthesize and implement the code.Generate and download the configuration file to an FPGA device.Steps involved in devolopment of software Processmodule car_detector_final( input [1:0] x,input clk,rst, output entry,exit,output [3:0] count );parameter s0=4'b0000;parameter s1=4'b0001;parameter s2=4'b0010;parameter s3=4'b0011;parameter s4=4'b0100;parameter s5=4'b0101;parameter s6=4'b0110;parameter s7=4'b0111;parameter s8=4'b1000;reg [3:0] state , next_state;always @ (posedge clk)beginif(rst) beginstate