finite state machines (fsm)finite state machines (fsm…dea.unsj.edu.ar/sisdig2/codificacion de mef...

FINITE STATE MACHINES (FSM)FINITE STATE MACHINES (FSM)

IN VHDL

C. Sisterna Spring 03 ECET - CET 486 - 586 1

State Machine General Diagram

Outputs

InputsNextStateL i

CurrentState

Ne t

OutputLogicLogic Logic

CurrentState

NextState

Logic

CLKRST

Style Clocked Process State Transition Output Process Diff tStyle Clocked Process State Transition Output Process

Style A

Style B

St l C

Different processes

Combined processes

Style C

Style D

C. Sisterna Spring 03 ECET - CET 486 - 586

State Machine: Declarative Part

Declare an enumerated data type

-- declare the (state-machine) enumerated type type FSM States is (RST, CNT, LOAD, OUT); type S _States s ( S , C , O , OU );

Declare signals of the enumerated data type

-- declare signals of FSM_States type signal current_state, next_state: FSM_States;

The only values that current state and next stateThe only values that current_state and next_state can hold are: RST, CNT, LOAD and OUT


State Machine: Clocked Process

• The clocked process decides when the state machine should change stateshould change state

• This process is activated by the state machine’s clock

• Depending on the present state and the value of the input signals, the state machine can change state at p g , gevery active clock edge

• Current state gets the value of the next state on the• Current state gets the value of the next state on the active edge of the clock

N t t t l i t d i th t t t iti• Next state value is generated in the state transition process, depending on the values of current state and the inputsthe inputs


State Machine: Combinatorial Process

• Assigns the output signals their value depending on the present statethe present state

• Next state logic and output logic is best modeled i t t t b tt f thiusing case statements are better for this process

• All the rules of combinatorial process have to be pfollowed to avoid generating unwanted latches

• For Mealy Machines if then else statement is used to• For Mealy Machines if-then-else statement is used to create the dependency between the current state, the input signal and output signal p g p g


State Machine: Reset behavior

• Asynchronous reset: ensure that the state machine is always initialized to a known valid state before theis always initialized to a known valid state, before the first active clock transition and normal operation commences

• No reset or a synchronous reset: there is no way to predict the initial value of the state register flip flopspredict the initial value of the state register flip-flops. It could power up and become permanently stuck in an uncoded state.


State Machine Style Descriptions in VHDL - Example

X = 1

Moore FSM

S1Z 1

S0Z 0 X = 0X = 0 Z = 1Z = 0 X 0X 0

X = 1X = 1

Mealy FSMX = 1

Z = 1

S1S0X = 0

Z = 1

X = 0Z = 0

X = 1

Z = 0


Style A - Moore State Machine

( X) ( lk )

Next State Logic Present State Logic Output Logic

process (state, X)begin

case state iswhen S0 => next_state <=..;when S1 > next State < ;

process (clk, rst)begin

if(rst = ‘1’) thenstate <= S0;

elsif (rising edge(clk))

process (state)begin

case state is OsIswhen S1 => next_State <=..;

end case;end process;

elsif (rising_edge(clk)) then

state <= next_state;end if;

end process;

when S0 => Z <= ... ;when S1 => Z <= ... ;

end case;end process;end process; p ;

Clock

Reset


Style A - Mealy State Machine

N t St t L i P t St t L i



if(rst = ‘1’) then


case state is

Next State Logic Present State Logic Output Logic

Is begincase state is

when S0 => next_state <=... ;when S1 => next_State <=... ;

end case;

if(rst = 1 ) thenstate <= S0;

elsif (rising_edge(clk)) thenstate <= next_state;

end if;

when S0 => if (X = ‘0’) thenZ <= ... ;

else Z <=... ;

end if;Os

Is


end if;end process;

end if;when S1 => if (X = ‘1’) then

.... ;else

.... ;end if;


ClockReset


Style A - Synthesis

Moore

Mealy


Style B - Moore State Machine

State, Next State and Output Logic

process(clk, rst)begin

if(rst = ‘1’) thenstate <= s0;

Is

state s0;Z <= ‘0’;

elsif (rising_edge(clk)) thencase state is

when S0 => Osnext_state <= .... ;

Z <= ... ;when S1 =>

next_state <= ... ;Z <= ... ;

end case;end if;

end process;

ClockReset


Style B - Mealy State Machine

process(clk, rst)begin

State, Next State and Output Logic

beginif(rst = ‘1’) then

state <= S0;Z <= ‘0’;

elsif (rising edge(clk)) thenelsif (rising_edge(clk)) thencase state is

when S0 =>next_state <= .... ;if (X=’0’) then

Isif (X 0 ) then

Z <= ... ;else

Z <= ... ;end if;

Os

;when S1 =>

next_state <= ... ;if (X = ‘1’) then

Z <= ... ;end if;

end case;end if;

end process;

ClockReset


Style B - Synthesis

MMoore

MealMealy


Style C - Moore State Machine

process (clk, rst)

Present State and Next State Logic

p ( , )begin

if(rst = ‘1’) thenState <= S0;

elsif (rising_edge(clk)) then process (state)

Output Logic

case state is when S0 =>

if(X =’1’) thennext_state <= ... ;

d if

process (state)begin

case state iswhen S0 => Z <= ... ;when S1 => Z <= .... ;

OsIsend if;

when S1 => if( X = ‘1’) then

next_state <= ... ;end if;

when S1 Z .... ;end case;

end process;

end if;end case;

end if;end process;

Clock

Reset


Style C - Mealy State Machine

process (clk rst) process (state X)

Present State and Next State Logic Output Logic


if(rst = ‘1’) thenstate <= S0;

elsif (rising edge(clk)) then


case state iswhen S0 =>

if(X=’1’) thenelsif (rising_edge(clk)) thencase state is

when S0 => if(X =’1’) then

next state <= ... ;

if(X= 1 ) thenZ <= ... ;

elseZ <= ... ;

end if;OsIs

next_state ... ;end if;

when S1 => if( X = ‘1’) then

next state <= ... ;

end if;when S1 =>

if(X=’1’) thenZ <= ... ;

else_ ;end if;

end case;end if;

end process;

Z <= ... ;end if;


Clock

Reset


Style C - Mealy State Machine

Moore

MealyMealy


Style D - Moore State Machine

OsNext State and Output Logic

P t St t L iprocess (state, X)begin

next_state <= state;case state is


Present State Logic

when S0 => if(X =’1’) then

next_state <= ... ;end if;


state <= S0;elsif (rising_edge(clk)) then

state <= next state;

Is

Z <= ... ;when S1 =>

if( X = ‘1’) thennext_state <= ... ;

d if

_ ;end if;

end process;

end if;Z <= ... ;


Clock

Reset


Style D - Mealy State Machine

( t t X)

OsNext State and Output Logic


next_state <= state;Z <= ... ;

case state isprocess (clk, rst)

Present State Logic

case state is when S0 =>

if(X =’1’) thennext_state <= ... ;Z <= ;


state <= S0;elsif (rising_edge(clk)) then

t t t t t

IsZ < ... ;

end if;when S1 =>

if( X = ‘1’) thennext state <= ... ;

state <= next_state;end if;

end process;

e t_state ;Z <= ... ;

end if;end case;

end process;

Clock

Reset


Style D - Mealy State Machine

Moore

Mealy


State Machine Directive, Attribute and Encoding Styles

S ti l

There are several way to encode an State Machine

- Sequential

- Gray Minimal number of FFs and wide combinatorial

functionsCPLD

- Binaryfunctions

Each state one FF - One-hot

- Two-hot

Narrow combinatorial functionsfunctions

FPGA


syn_encoding - Synplify

Override the default FSM Compiler encoding for a FSM

P ibl lPossible values:

• Default: assign an encoding style based on the number of states:

• Sequential for 0 - 4 enumerated typesq yp

• One-hot for 5 - 24 enumerated types

• Gray for > 24 enumerated types

• Sequential: 000 001 010 011 100 101 110 111q

• One-hot: 001 010 100

• Gray: 000 001 011 010 110 111 101 100

• Safe: default encoding + reset logic to a known stateC. Sisterna Spring 03 ECET - CET 486 - 586

g g

syn_encoding - Synplify

-- declare the (state-machine) enumerated type

Syntax (source code)

type my_state_type is (SEND, RECEIVE, IGNORE, HOLD, IDLE);-- declare signals as my_state_type typesignal nxt_state, current_state: my_state_type;_ _ _ _-- set the style encodingattribute syn_encoding of current_state: signal is value;

syn_encoding in SCOPE


type_encoding_style - LeonardoSpectrum

Possible values:

• Binary

Onehot• Onehot

• Twohot

• Gray

• Random

Declare the (state machine) enumerated type-- Declare the (state-machine) enumerated typetype my_state_type is (SEND, RECEIVE, IGNORE, HOLD, IDLE);-- Set the TYPE_ENCODING_STYLE of the state type

tt ib t TYPE ENCODING STYLE f t t t t i ONEHOTattribute TYPE_ENCODING_STYLE of my_state_type:type is ONEHOT;


type_encoding - LeonardoSpectrum

type_encoding allows to fully control the state di h d d th t t d i th dencoding hard code the state code in the source code

-- Declare the (state-machine) enumerated typetype my_state_type is (SEND, RECEIVE, IGNORE, HOLD, IDLE);-- Set the type_encoding attributeattribute type_encoding of my_state_type:type is

("0001","01--","0000","11--","0010");

StateState Table

Note: LeonardoSpectrum allows to use ‘-’. It can be used to reduce the size of the circuit


State Machine Coding: Residual States

• If one-hot state coding is not used, the maximum o e o s a e cod g s o used, e a unumber of states is equal to 2**N, where N is the vector length of the state vector

• In state machines where not all the states are used, there are three options:p

Let “chance: decide what is to happen if the machine goes to an undefined state

Define what is to happen if the state machine goes to an undefined state by ending the case statement with when others

Define all the possible states in the VHDL code


finite state machines (fsm)finite state machines (fsm…dea.unsj.edu.ar/sisdig2/codificacion de mef...

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