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What are PLDs?

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Programmable Logic Devices

• A pre-fabricated ASIC capable of performing any logic subject to user programming

• compromise between the semi-custom ASICs and standard components

• a collection of logic elements placed in a programmable interconnection framework

• fast design turn around time

• field programmable EPROM, E2PROM, Flash, SRAM based

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PLD Programmability (1)

• programmable combinational logic PT-based, LUT

LUT(look-up

table)

PT-based building block• 2-level logic, high fan-in

LUT-based building block• 4-5 inputs, fine-grain arch.• ROM like

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PLD Programmability (2)

• programmable register register type, register control

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PLD Programmability (3)

• programmable interconnect routing resources including switching elements,

local/global lines, clock buffers

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PLD Programmability (4)

• programmable I/O direction, I/O register, 3-state, slew rate

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Field Programmability

• can verify designs at any time by configuring the FPGA/ CPLD devices on board via the download cable or hardware programmer

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PLD Classifications

• General classification Simple programmable logic device (SPLD) Complex programmable logic device (CPLD) Field programmable gate array (FPGA)

• Classification by programming technology Fuse, anti-fuse (OTP) EPROM, EEPROM, Flash (multiple programming) SRAM (volatile, need configuration when power up)

• Classification by routing structures Segmented (incremental) routing Continuous routing

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Simple PLD

• Programmable AND/OR array Sum-Of-Product (SOP) to implement Boolean

functions

• facilitated with FFs, output macros, and feedback path

• foldback architecture

• low density, low cost, fixed delay

• examples: PAL, GAL, PEEL, FPLA

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PAL Architecture

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Complex PLD architecture

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Field Programmable Gate Array

• architecture originates from gate array• 2-D array of programmable logic blocks (cells)• programmable / incremental interconnect• less predictable timing, place &routing is

crucial• matrix based architecture

Xilinx XC4000, Spartan, Virtex, QuickLogic

• Row based architecture Actel ACT families

• Continuous interconnect architecture Altera Flex 8K/10K, APEX

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Generic FPGA logic cell

Carrylogic

Look-UpTable(RAM)

Macro-cell

I/Ocells

Mcell

PrimaryInputs

Logic cell

16X1

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Continuous v.s. Segmented

CROSSBAR

continuous segmented

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Rapid Prototyping & System Verification

• To see is to believe

• The ASIC respin cost is too high

• Verification at lower speed

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Low cost solution of FPGAs

• Hardcopy technology Reduced die area

Only two mask layer cost

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Latest FPGA Features

• Advanced process For example, Xilinx Spartan III use 90nm process

Next generation Virtex FPGA will contain 1G transistors in 70nm process

• High logic gate count Up to millions of logic gates

• Large on chip memory From several K bits to several M bits

• On chip processor ARM 7/9, PowerPC

• On chip multiplier/DSP

• High speed I/O Up to 3.125Gbps

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What’s inside?

• Altera Excalibur Processor +

Memory +

1,000,000 plus

logic capacity

PLD Area for Customer Design

ARM922TCore

Single-PortRAM

Dual-PortRAM

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SoPC example

EBI Bridge

SRAM(Single Port)

SDRAMController

DPRAM

SDRAM Interface

FlashInterface

ARMProcessorP

LL

s

Stripe

33-MHz Utopia-2

PHYManager

CustomLogic

AMBABus

Inter-face

Master Port

Slave Port

Dual-Port RAM Interface

Logic

Ethernet Controller

MediaIndependentInterface

AMBABus

Inter-face

AMBABus

Inter-face

ATM Cell ProcessorNios

CPU

PCIController

PCIAMBABus

Inter-face

Bridge