fpga(field programming gate array)

8/3/2019 FPGA(Field Programming Gate Array)

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FPGAs are "fine-grain" devices -that means thatthey contain a lot (up to 1,000,00) of tiny blocks

of logic with flip-flops. FPGAs are built from onebasic "logic-cell", duplicatedhundreds or thousands of time.


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It is two dimensional array of logic blocks andflip-flops with a electrically programmableinterconnections between logic blocks . The

interconnections consist of electricallyprogrammable switches which is why FPGAdiffers from Custom ICs, as Custom IC isprogrammed using integrated circuit

fabrication technology to form metalinterconnections between logic blocks


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Systems typically consisted of few large scale integratedcomponents and large number of SSI (small scale integratedcircuit) and MSI (medium scale integrated circuit)components. Initial attempt to solve this problem led todevelopment of Custom ICs which were to replace the large

amount of interconnect. This reduced system complexityand manufacturing cost, and improved performance.However, custom ICs have their own disadvantages. Theyare relatively very expensive to develop, and delayintroduced for product to market (time to market) becauseof increased design time. Logic block in an FPGA can be

implemented in ways that differ in number of inputs andoutputs amount of area consumed, complexity of logicfunctions that it can implement, total number of transistorsthat it consumes.


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logic blocks are made using transistor, mux,etc . It varies from one to other.

Cross point FPGA

Plessey FPGA

Actel Logic Block

Xilinx Logic block

Altera Logic Block


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Size of logic block plays an important role indeciding density of logic blocks and areautilization in an FPGA. It also effects theperformance of the FPGA.

A large size logic block implements more logic andhence requires less number of logic blocks toimplement a functionality on the FPGA. On theother hand a large logic block will consume more

space on the FPGA. So optimal size of logic blockis one that optimally uses lesser number of logicblocks for functionality implementation whileconsuming as little space as possible.


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Typically an FPGA has logic blocks,interconnects and Input / Output blocks. InputOutput blocks lie in the periphery of logic

blocks and interconnect. Wire segmentsconnect I/O blocks to wire segments throughconnection blocks. Connection blocks areconnected to logic blocks, depending on the

design requirement one logic block isconnected to another and so on.


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Xilinx Routing architecture :In Xilinx routing,connections are made from logic block into thechannel through a connection block.

Actel routing methodology : Actel 's design hasmore wire segments in horizontal directionthan in vertical direction

Altera routing methodology : Altera routing

architecture has two level hierarchy. At the firstlevel of the hierarchy, 16 or 32 of the logicblocks are grouped into a Logic Array Block


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There is a constant effort on the part of systemdesigners to design systems with improvedperformance, efficiency and flexibility .Today, ifone wants to make effective and competitive use of

these general purpose blocks, then one of thebetter ways is to user configurable hardware thatallows user programmability. The first form ofreconfigurable device was Programmable LogicDevices which consisted of arrays of AND and OR

gates with programmable metal paths asinterconnection between them. They could beprogrammed to into a single chip to meet specificrequirements. PLDs later evolved into what waslater known as FPGAs.


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On the basis of internal arrangement of blocks FPGAs can bedivided into three classes:

1. Symmetrical arrays :This architecture consists of logic elements(called CLBs) arrangedin rows and columns of a matrix and interconnect laid out

between them.

2. Row Based architecture:Row based architecture consists of alternating rows of logic

modules and programmable interconnect tracks. Input outputblocks are located in the periphery of the rows. One row may be

connected to adjacent rows via vertical interconnect.3. Hierarchical PLDs :

This architecture is designed in hierarchical manner with top levelcontaining only logic blocks and interconnects.


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At this stage designer has to decide whatportion of his functionality has to beimplemented on FPGA and how to integrate

that functionality with rest of the system.Belowgiven circuit consists of gates and flip flops.Combinational elements of the circuit arecovered by a 4-input Look up table(4-LUT).Sequential elements in the input circuitmap to flip flops on the FPGA. Placement ofthese elements is done in such a way as tominimize wiring during routing.


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fpga(field programming gate array)

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