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Gate array design

• Use a sea of basic transistors (pmos/nmos) or gates (NAND/NOR)

• Can have cells which can provide a universal logic function

• Just need to add signal routing – only a few masksAdvantages:• Reduced design time• Less chance of errors• Reduced production costs• Decrease time to product

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www.geocities.com/aps_ipu

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Gate Array Design (Cont.)

Disadvantages:

• Very Limited flexibility

• Need moderately high volume product

• Less easily protected IPR

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Programmable design

• Use an array of logic cells

• Cells can provide a universal logic function

• Signal routing through switch box approach

• RAM holds routing patterns (re-programmable)

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Advantages:• Reduced design time• Easily reworked• Low design costs• Decrease time to productDisadvantages:• Limited flexibility• Low volume production• Less easily protected IPR

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Programmable Logic Devices (PLDs)

Programmable logic device, or PLD, is a general name for a digital integrated circuit

• capable of being programmed to provide a variety of different logic functions.

There are four main families of PLDs:- Programmable logic arrays (PLA)- Programmable array logic devices (PAL)- Read-only memories (ROM)- Complex PLDs (FPGAs, RAM)

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• Programmable switches allow connections to be made in an array of logic gates. We will look at the operation of each and examples of combinatorial and sequential design with each.

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Programmable Logic Devices (PLDs)

What are the advantages of programmable logic devices?

• simple PLDs can realise from 2 to 10 functions of 4 to 16 variables on a

• single integrated circuit• excellent for prototyping designs• it is possible to replace a number of SSI devices

with a single device to• realise logic networks

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• single chip required to implement (possibly large) logic designs

• complex PLDs can be used realise complex digital systems– even processors!

• PLDs allow us to simplify designs and reduce development times– hence reduced overheads!

• changes in the design can be easily implemented by reprogramming the device

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Programmable Technology

Fusible link devices - e.g. the PROM- Blowing a fuse breaks a link between lines- Once programmable- Very high density possible

Electrical switching elements - e.g. the EPROM, EEPROM• nMOS transistors used to ‘switch’ connections between

lines• Devices can be re-programmed• Relatively high density• How do we program PLDs?

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Structure of PAL

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Layout of a part of a Programmable Logic Cell

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Structure of a FPGA

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Configuration of Memory Cell

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Configuration of Xilinx 300

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Programmable I/O

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General Purpose Interconnect

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Direct Interconnect

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Vertical and Horizontal long line

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EPROM Programmable Switches

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Actel antifuse structure

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Altera 700 Logic Array Blocks

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Xilinx 7000 CLB

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References1. S. Brown, R. Francis, J. Rose, Z. Vranesic, Field-

Programmable Gate Arrays, Kluwer Academic Publishers, May 1992.

2. S. Trimberger, Ed., Field-Programmable Gate Array Technology, Kluwer Academic Publishers, 1994.

3. J. Rose, A. El Gamal, A. Sangiovanni-Vincentelli, “Architecture of Field- Programmable Gate Arrays,” in Proceedings of the IEEE, Vol. 81, No. 7, July 1993, pp. 1013-1029.

4. J. Oldfield, R. Dorf, Field Programmable Gate Arrays, John Wiley & Sons, New York, 1995.

5. C.H.Roth, DSD with VHDL, Thomson Learning