product design methodology - soi industry...

1 SOI Industry Consortium – 2018

Product Design Methodology

2018 – Tokyo

Christophe Tretz, Carlos Mazure


Agenda

SOI Industry Consortium

SoC design approach

Design considerations

Conclusions


2014 FD-SOI

Where’s the supply chain?

3


2018 FD-SOI

Substrates: production

Foundry: production

IP: good enough and improving

The Ecosystem is ready

Focus: Applications and Products

4


SoC Design Approach


Design flowD

esig

n F

low

Architectural design

Functional/Logic design

Circuit design

Physical design

Physical verification and

signoff

System Specification

Fabrication

Packaging and testing

Chip

• Starting a new design will go

through all the steps from

system specification to

manufacturing and testing.


Design flowD

esig

n F

low



Circuit design

Physical design


signoff


Fabrication


Chip

•

•Using FD-SOI, the following

steps could take advantage of

the technology, either through

performance estimation (blue)

or bias connections (orange)


Design flowD

esig

n F

low



Circuit design

Physical design


signoff


Fabrication


Chip

•

•

• It is not necessary to optimize

an SoC design at every stage,

but improvements can be

obtained progressively


Case 1: Simple digital SoC

• All digital SoC, using basic library

blocks, with some specialized

proprietary logic– Most standards blocks are already available in foundry libraries

– Recompile the proprietary logic with or without back bias optimization

– Benefit savings from the existing optimized blocks

• Using this approach, significant

power savings can be achieved by

reusing existing blocks and doing

minor recompile

De

sig

n F

low



Circuit design

Physical design


signoff


Fabrication


Chip


Case 2: RF – Mixed signal chip

• While this type of design likely

need to do a full circuit design and

physical design, they are usually

“small” and easier to control

• Turnaround time can be relatively

small with significant savings in

power

• Example: AnalogBits SERDES

– ”remap” completed in 3 months

– minimum layout fixes

– greatly improved performance!!!

De

sig

n F

low



Circuit design

Physical design


signoff


Fabrication


Chip


Case X: fully optimized SoC

• Sometimes a full optimization is

desired, and some design can benefit

from all the advantages of FD-SOI

• Architecture and logic can be further

optimized and changed to take into

account back bias

• This approach will take the most

design time, but can be done in

parallel with a faster turnaround

design

• Most dramatic power improvements!!

De

sig

n F

low



Circuit design

Physical design


signoff


Fabrication


Chip


A short history of circuit design


Why looking at the past?

• The SOI Consortium is often asked how difficult it is to use FD-SOI in

designs

• Many circuit design techniques were created BC (Before CMOS),

without even going to “prehistoric” eras of circuit design (think TTL,

ECL, etc)

• The same basic design guidelines still apply, maybe more than ever

• Circuit design techniques evolved into what is CMOS design

• And, maybe designing with back gate bias is not such a new thing

• We can all learn from the past and why people designed a certain way

• There are always new ways to use something, and several talks from

past SOI Consortium events have shown such techniques (Andrea’s,

Borat’s presentations are great example of what can be done)


Enhancement/Depletion mode MOS design

• Overview:– Logic high is only Vdd – Vth (enhancement only, full swing with depletion device load)

– Fabrication of both types of devices is tricky

– BUT: still “better” than any type of ECL or TTL design!

• Solutions:

– “Improve” the load devices (Bootstrapped nMOS, depletion, pMOS)

• Using back gate biasing to change operation mode


Intel 4004

The Intel 4004 is a 4-bit central processing

unit (CPU) released by Intel Corporation in 1971.

It was the first commercially available

microprocessor by Intel,[2]and the first in a long

line of Intel CPUs.

The 4004 employs a 10 µm process silicon-

gate enhancement load pMOS technology

on a 12 mm² die

https://en.wikipedia.org/wiki/Intel_4004#cite_note-2


Pseudo nMOS

• The “logic” evolution from nMOS logic to logic with nMOS/pMOS

• Large ratio between respective device performance made CMOS area

prohibitive

• Pseudo nMOS reduce the gate loading significantly

• Clocking/dynamic logic is a direct improvement on pseudo nMOS


Domino and Zipper (NORA) logic

• Domino logic is fast, but inverters are needed

• Zipper logic removes the need of inverters and solve some charge sharing

and charge leakage issues


Why did I go over those logic design styles?

• Design has evolved over time

• Many design choices were related to what was available

at the time, and trade offs were made to compensate

relative performance or manufacturing shortcomings

• FD-SOI offers new opportunities, but also allows to go

back to past decisions

– For example, having a “stronger” pMOS load would remove some drawbacks from having a pMOS load (pseudo nMOS) or a pMOS pullup network (zipper)

– Depletion/enhancement devices mix offered some interesting construct (forward/reverse bias do too…)


• Body biasing is not really new

• First order, body biasing is not a mandatory design option;

a fixed value can be used and the various EDA tools

available will take care of the implementation/verification

• Body biasing offers many design options and design

philosophies

What about body biasing?


Body Biasing – Leveraging for Market Leadership

• Vdd Overdrive Only

• SOG Global Body Biasing

• Independent Domain Body Biasing

• On Chip Memory Array Body Biasing

• Assymetric Device Body Biasing

• Mixed Vt Common Well Body Biasing

Courtesy – Ron Martino, NXP – SOI Consortium Silicon Vally 2018


Back gate bias: an additional performance boost knob

• Current high performance SoC/microprocessors use Vdd

to alter performance– Increasing Vdd will improve speed/overall performance but will also increase consumed power

– By decreasing Vdd (or turning it off), you can enter a sleep/lower power mode (or turning off unused parts of the SoC

• Back gate biasing offers more tuning options

– You can use both Vdd and various back gate bias values to either improve performance even more

– You can also use both Vdd and other back gate bias values to improve overall performance while not increasing power as much

– You can use other back gate bias values to enter low Vdd operation mode and enable low power performance


Conclusions

• The ecosystem has been ready and there are many ways to approach

designing with FD-SOI

• We do not need to reinvent the wheel!!! A lot of solutions are there already

even if we have to look in the past.

•There is more than one way to use back gate bias!!

• Finally, do not hesitate to contact the Consortium! We are here to help

you!


Backup slides


Remap example: AnalogBits

Courtesy: AnalogBits - SOI Consortium – April 2016


Remap example: AnalogBits

ANALOG BITS achieved this work in about 3 months!!!

Courtesy: AnalogBits - SOI Consortium – April 2016

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