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Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power ConstraintSeong-Ook Jung, Ki-Wook Kim and

Sung-Mo (Steve) Kang DATE’02

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Outline

Introduction Simulation Results on Four

Feasible Configuration Dual Vt Domino Logic Synthesis

Flow

Experimental Results Conclusions

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Introduction

Domino logicClock=0 : precharge

Clock=1 : discharge(evaluate)

Advantages : high performance

Drawback : noise sensitive

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Introductionnoise

Solution : increase keeper size

Drawbacks : 1. increase power consumption

2. increase evaluation time

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Introduction

Vt (threshold voltage)

Vt

But exponential increase in subthreshold leakage current(Isub) of transistors.

performance

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Introduction Tradeoff

Vt evaluation time Isub

keeper size power consumption evaluation time

Goal use low vt devices to speedup

evaluation while maintaining power consumption and noise constraint.

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Four Feasible Configuations

low vt assignment to NMOS tree and/or PMOS transistor of output inverter.

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Keeper Sizing for Feasible Configurations

Increase keeper size (width) to satisfy noise constraint

Noise Constraint Topmost NMOS transistors directly

connected to 20% of Vdd Other NMOS transistors turn on with Vdd Fail if the output voltage of inverter is

greater than 10% of Vdd

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Keeper Sizing for Feasible Configurations

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Evaluation Time(tE) and Powernormalized by HH type of each gate with 4:1 P:N ratio output inverter.

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Power consumption in active mode

1. analyze the simulation result of domino logic gate with 4:1 P:N ratio output inverter.

(1) LL type : fastest speed, highest power consumption(2) OR gate : LH slower than HL; Pact of LH greater than HL(3) AND gate : HL slower than LH; Pact is almost the same

2. analyze the effect of up-sizing PMOS transistor from 4:1 to 8:1.

tE is improved by increasing the P:N ratio of output inverter(1) OR gate : tE of LL are almost the same(2) OR gate : Pact increases(3) AND gate : Pact almost the same

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Leakage current in standby mode

normalized by HH type of each gate with 4:1 P:N ratio output inverter.

Ileak is masured in standby mode

by making all logic gates evaluated to reduce leakage

Ileak is determined by precharge PMOSand NMOS of output inverter (the same size and Vt)

Ileak is almost the same for all simulation case

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Dual Vt Domino Logic Synthesis Flow

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Type selection forunmarked logic gateswith power constraint(LL, LH and HL type)

Dual Vt Domino Logic Synthesis Flow

For each gate in the critical paths, a proper type is selected for delay minimization with power constraint.

Example:OR gate : LL, HL, LH, HHAND gate : LL,LH,HL, HH

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Dual Vt Domino Logic Synthesis Flow

Gate selection based onperformance sensitivity

A gate is chosen such that performance of the gate ismaximum.

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Experimental Results

tE- denotes critical path speed-up.(with respect to the initial circuits HH)Pact+denotes total active power overhead.(with respect to the initial circuits HH)

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Experimental Results Bold numbers : maximum speed-up for

each benchmark circuit(maximum speed up range from 15.91% to 18.62% with 0.38% to 7.01% active power increase)

Half of benchmark circuits achieve around 18% speed-up with less than 1% active power increase

The average maximum speed up is 17.43% with 1.84% average active power increase.

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Conclusions

Tradeoffs need to be made among noise , power, and performance.

Propose a dual Vt synthesis method for high performance with noise (keeper sizing) and power constraint.