domino logic - university of california,...

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EECS141 1Lecture #22

EE141EE141--Fall 2007Fall 2007Digital Integrated Digital Integrated CircuitsCircuits

Lecture 22Lecture 22Domino LogicDomino LogicPower RevisitedPower Revisited

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AnnouncementsAnnouncementsProject phase two due next Tuesday

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Class MaterialClass Material

Last lectureAdders

Today’s lectureDomino logicRevisit power

ReadingChapter 6, Chapter 7

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Domino LogicDomino Logic

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Domino LogicDomino Logic

In1

In2 PDNIn3

Me

Mp

Clk

Clk Out1

In4 PDNIn5

Me

Mp

Clk

ClkOut2

Mkp

1 → 11 → 0

0 → 00 → 1

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Why Named Domino?Why Named Domino?

Clk

Clk

Ini PDNInj

IniInj

PDN Ini PDNInj

Ini PDNInj

Like falling dominos!

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Properties of Domino LogicProperties of Domino Logic

Only non-inverting logic can be implementedVery high speed

static inverter can be skewed, only L-H transition criticalInput capacitance reduced – smaller logical effort

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Domino Logic LEDomino Logic LE

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Domino Logic LE (skewed static gate)Domino Logic LE (skewed static gate)

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Buffer Buffer ““AverageAverage”” LELE

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Optimal EF/stage with DominoOptimal EF/stage with DominoDomino buffers are faster than static CMOS invertersIs optimal EF/stage for a chain of domino gates still 4?

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Designing with Domino LogicDesigning with Domino Logic

Mp

Me

VDD

PDN

Clk

In1In2In3

Out1

Clk

Mp

Me

VDD

PDN

Clk

In4

Clk

Out2

Mr

VDD

Inputs = 0during precharge

Can be eliminated

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Footless DominoFootless Domino

The first gate in the chain needs a foot switchPrecharge is rippling – short-circuit current

VDD

Clk Mp

Out1

In1

1 0

VDD

Clk Mp

Out2

In2

VDD

Clk Mp

Outn

InnIn3

1 0

0 1 0 1 0 1

1 0 1 0

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Can mitigate short-circuit current by alternating between footed and unfooted domino

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To eliminate the short-circuit current, can delay the clock for each stage

VDD

Clk Mp

Out1

In1

1 0

VDD

Clk Mp

Out2

In2

VDD

Clk Mp

Outn

InnIn3

1 0

0 1 0 1 0 1

1 0 1 0

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Differential (Dual Rail) DominoDifferential (Dual Rail) Domino

A

B

Me

Mp

Clk

ClkOut = AB

!A !B

MkpClk

Out = ABMkp Mp

Allows inverting gates to be built

1 0 1 0

onoff

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npnp--CMOSCMOS

In1

In2 PDNIn3

Me

Mp

Clk

Clk Out1

In4 PUNIn5

Me

MpClk

Clk

Out2(to PDN)

1 → 11 → 0

0 → 00 → 1

Only 0 → 1 transitions allowed at inputs of PDN Only 1 → 0 transitions allowed at inputs of PUN

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NORA LogicNORA Logic

In1

In2 PDNIn3

Me

Mp

Clk

Clk Out1

In4 PUNIn5

Me

MpClk

Clk

Out2(to PDN)

1 → 11 → 0

0 → 00 → 1

to otherPDN’s

to otherPUN’s

Fast, but EXTREMELY sensitive to noise!

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Power Power RevisitedRevisited

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Transition Activity and PowerTransition Activity and PowerEnergy consumed in N cycles, EN:

EN = CL • VDD2 • n0→1

n0→1 – number of 0→1 transitions in N cycles

fVCN

nfNEP DDLN

NNavg ⋅⋅⋅⎟

⎠⎞

⎜⎝⎛=⋅= →

∞→∞→

210limlim

fN

nN

⋅= →

∞→→10

10 limα

fVCP DDLavg ⋅⋅⋅= →2

10α

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“Dynamic” or timing dependent component

Type of Logic Function (NOR vs. XOR)“Static” component (does not account for timing)

Circuit Topology

Type of Logic Style (Static vs. Dynamic)

Signal StatisticsInter-signal Correlations

Signal Statistics and Correlations

Factors Affecting Transition ActivityFactors Affecting Transition Activity

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Type of Logic Function: NORType of Logic Function: NOR

011001010100

OutBA

Example: Static 2-input NOR Gate

Assume signal probabilitiespA=1 = 1/2pB=1 = 1/2

Then transition probabilityp0→1 = pOut=0 x pOut=1

= 3/4 x 1/4 = 3/16

α0→1 = 3/16

If inputs switch every cycle

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Type of Logic Function: NANDType of Logic Function: NAND

011101110100

OutBA

Example: Static 2-input NAND Gate



=

α0→1 =

If inputs switch every cycle

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Type of Logic Function: XORType of Logic Function: XOR

011101110000

OutBA

Example: Static 2-input XOR Gate



= 1/2 x 1/2 = 1/4

α0→1 = 1/4

If inputs switch in every cycle

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Power Consumption of Dynamic GatesPower Consumption of Dynamic Gates

In1

In2 PDNIn3

Me

Mp

CLK

CLKOut

CL

Power only dissipated when previous Out = 0

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Dynamic Power Consumption is Dynamic Power Consumption is Data DependentData Dependent

011001010100

OutBA

Dynamic 2-input NOR Gate

Assume signal probabilitiesPA=1 = 1/2PB=1 = 1/2

Then transition probabilityP0→1 = Pout=0 x Pout=1

= 3/4 x 1 = 3/4

Switching activity always higher in dynamic gates!P0→1 = Pout=0

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Vdd

I

I

Vdd

IN

INB

OUTB OUT

Guaranteed transition for every operation!

α0->1 = 1

DualDual--Rail DominoRail Domino

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ClockClock

Always switchesOften consumes 25-50% of total powerClock gating commonly employed

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Problem: Problem: ReconvergentReconvergent FanoutFanout

A

B

X

Z

Reconvergence

P(Z = 1) = P(B = 1) . P(X = 1 | B=1)

Becomes complex and intractable fast

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InterInter--Signal CorrelationsSignal Correlations

Logic withoutreconvergent fanout

Logic with reconvergent fanout

A

BZ

CA

Z

C

B

p0→1 = (1 – pApB) pApBP(Z = 1) = p(C=1 | B=1) p(B=1)

p0→1 = 0

Need to use conditional probabilities to model inter-signal correlationsCAD tools best for performing such analysis

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GlitchingGlitching in Static CMOSin Static CMOSA

B

X

CZ

ABC 101 000

X

Z

Gate DelayAlso known as

dynamic hazards

The result is correct,but there is extra power dissipated

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Example: Chain of NAND GatesExample: Chain of NAND Gates1

Out1 Out2 Out3 Out4 Out5

0 200 400 6000.0

1.0

2.0

3.0

Time (ps)

Volta

ge (V

)

Out8Out6

Out2

Out6

Out1

Out3

Out7

Out5

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Principles for Power ReductionPrinciples for Power ReductionMost important idea: reduce wasteExamples:

Don’t switch capacitors you don’t need to– Clock gating, glitch elimination, logic re-structuring

Don’t run circuits faster than needed– Power α VDD

2 – can save a lot by reducing supply for circuits that don’t need to be as fast

– Parallelism falls into this category

Let’s say we do a good job of that – then what?

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Energy Energy –– Performance SpacePerformance Space

Plot all possible designs on a 2-D planeNo matter what you do, can never get below/to the right of the solid line

This line is called “Pareto Optimal Curve”Usually (always) follows law of diminishing returns

Performance

Ener

gy/o

p

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Optimization PerspectiveOptimization Perspective

Instead of metrics like EDP, this curve often provides information more directly

Ex1:What is minimum energy for XX performance?Ex2: Over what range of performance is a new technique (dotted line) actually beneficial?

Performance

Ener

gy/o

p

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Key ObservationKey ObservationDefine the Energy/Performance sensitivity of parameter, for example:

At optimal point, sensitivities to all parameters should be the same (ignoring constraints)

Must equal slope of the Pareto optimal curveOtherwise, could trade one parameter for another and end up with lower energy at same performance

T

TV

T

Energy VSPerf V

∂ ∂=∂ ∂DD

DDV

DD

Energy VSPerf V

∂ ∂=∂ ∂

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Why This Matters for Circuit DesignWhy This Matters for Circuit DesignDon’t really believe that should use sensitivities to calculate how to design your circuits:

Except for simple examples, CAD tools much better at doing that

Real reasons:Sensitivities tell you where in the space you are sitting:

– High sensitivity – pushing performance hard– Low sensitivity – not much lower energy to be gotten

Get rough idea of what happens if changed operating point by a small amountMore in EE241

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