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EE141 1 EE141 EECS141 1 Lecture #22 EE141-Fall 2012 Digital Integrated Circuits Lecture 22 Domino Logic EE141 EECS141 2 Lecture #22 Announcements Project phase 2 due Friday Phase 3 out this Friday Homework #8 out next Tues., due following Tues. EE141 EECS141 3 Lecture #22 Class Material Last lecture Multipliers Today’s lecture Domino logic Reading Chapter 7 EE141 EECS141 4 Lecture #22 Domino Logic EE141 EECS141 5 Lecture #22 Domino Logic In 1 In 2 PDN In 3 M e M p Clk Clk Out1 In 4 PDN In 5 M e M p Clk Clk Out2 M kp 1 1 1 0 0 0 0 1 EE141 EECS141 6 Lecture #22 Why Named Domino? Clk Clk In i PDN In j In i In j PDN In i PDN In j In i PDN In j Like falling dominos!

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  • EE141

    1

    EE141EECS141 1Lecture #22

    EE141-Fall 2012Digital Integrated Circuits

    Lecture 22Domino Logic

    EE141EECS141 2Lecture #22

    AnnouncementsProject phase 2 due Friday Phase 3 out this Friday

    Homework #8 out next Tues., due following Tues.

    EE141EECS141 3Lecture #22

    Class Material

    Last lecture Multipliers

    Today’s lecture Domino logic

    Reading Chapter 7

    EE141EECS141 4Lecture #22

    Domino Logic

    EE141EECS141 5Lecture #22

    Domino Logic

    In1In2 PDNIn3

    Me

    Mp

    Clk

    Clk Out1

    In4 PDNIn5

    Me

    Mp

    Clk

    ClkOut2

    Mkp1 11 0

    0 00 1

    EE141EECS141 6Lecture #22

    Why Named Domino?

    Clk

    Clk

    Ini PDNInj

    IniInj

    PDN Ini PDNInj

    Ini PDNInj

    Like falling dominos!

  • EE141

    2

    EE141EECS141 7Lecture #22

    Properties of Domino Logic

    Only non-inverting logic can be implemented Very high speed static inverter can be skewed, only L-H transition

    critical Input capacitance reduced – smaller logical effort

    EE141EECS141 8Lecture #22

    Domino Logic LE

    EE141EECS141 9Lecture #22

    Domino Logic LE (skewed static gate)

    EE141EECS141 10Lecture #22

    Buffer “Average” LE

    EE141EECS141 11Lecture #22

    Optimal EF/stage with DominoDomino buffers are faster than static

    CMOS inverters Is optimal EF/stage for a chain of domino

    gates still 4?

    EE141EECS141 12Lecture #22

    Example

  • EE141

    3

    EE141EECS141 13Lecture #22

    Designing with Domino Logic

    Mp

    Me

    VDD

    PDN

    Clk

    In1In2In3

    Out1

    Clk

    Mp

    Me

    VDD

    PDN

    Clk

    In4

    Clk

    Out2

    Mr

    VDD

    Inputs = 0during precharge

    Can be eliminated

    EE141EECS141 14Lecture #22

    Footless Domino

    The first gate in the chain needs a foot switchPrecharge is rippling – short-circuit current

    VDD

    Clk MpOut1

    In11 0

    VDD

    Clk MpOut2

    In2

    VDD

    Clk MpOutn

    InnIn31 0

    0 1 0 1 0 1

    1 0 1 0

    EE141EECS141 15Lecture #22

    Footless Domino

    Can mitigate short-circuit current by alternating between footed and unfooted domino

    EE141EECS141 16Lecture #22

    Footless Domino

    To eliminate the short-circuit current, can delay the clock for each stage

    VDD

    Clk MpOut1

    In11 0

    VDD

    Clk MpOut2

    In2

    VDD

    Clk MpOutn

    InnIn31 0

    0 1 0 1 0 1

    1 0 1 0

    EE141EECS141 17Lecture #22

    Differential (Dual Rail) Domino

    A

    B

    Me

    Mp

    Clk

    ClkOut = AB

    !A !B

    Mkp ClkOut = AB

    Mkp Mp

    Allows inverting gates to be built

    EE141EECS141 18Lecture #22

    np-CMOS

    In1In2 PDNIn3

    Me

    Mp

    Clk

    Clk Out1

    In4 PUNIn5

    Me

    MpClk

    Clk

    Out2(to PDN)

    1 11 0

    0 00 1

    Only 0 1 transitions allowed at inputs of PDN Only 1 0 transitions allowed at inputs of PUN

  • EE141

    4

    EE141EECS141 19Lecture #22

    NORA Logic

    In1In2 PDNIn3

    Me

    Mp

    Clk

    Clk Out1

    In4 PUNIn5

    Me

    MpClk

    Clk

    Out2(to PDN)

    1 11 0

    0 00 1

    Fast, but EXTREMELY sensitive to noise!

    EE141EECS141 20Lecture #22

    Next Lecture

    Flops and Latches