iii-v/ge channel engineering for future cmos 215th ecs meeting, san francisco, may 28, 2009 mark a....

III-V/Ge Channel Engineering for Future

CMOS

215th ECS Meeting, San Francisco, May 28, 2009

Mark A. Wistey

University of California, Santa BarbaraNow at University of Notre Dame

[email protected], 805-893-3279

U. Singisetti, G. Burek, A. Baraskar, V. Jain, B. Thibault, A. Nelson, E. Arkun, C. Palmstrøm, J. Cagnon, S. Stemmer, A. Gossard, M. RodwellUniversity of California Santa Barbara

P. McIntyre, B. Shin, E. KimStanford UniversityS. BankUniversity of Texas Austin Y.-J. LeeIntel Funding: SRC

mailto:[email protected]

2M. Wistey, Spring ECS 2009

Outline: Channels for Future CMOS

• FET scaling requirements... and failures

• Motivation for Regrown MOSFETs

• III-V Benefits and Challenges

• Fabrication Process Flow

• Depletion-mode MOSFETs

• The Shape of Things to Come

M. Wistey, Spring ECS 2009

Future CMOS Priorities

High drive current Id / Wg for wiringLow gate delay CFET∆V/Id for local

Low Parasitics

Capacitance – already 1-2 fF/µmResistance – already ~50% Rtot

Leakage Currents – now 50% power

Graphics: Mark Rodwell

High Performance

High packing density –width & contacts smallGrowable on Si substrates

Compatible with Existing CMOS


Simple FET ScalingGoal double transistor bandwidth when used in any circuit → reduce 2:1 all capacitances and all transport delays

→ keep constant all resistances, voltages, currents

reduce 2:1 all lengths, widths, thicknesses

✓gm , Id held constant

held constant ✓

(doubles mA/μm, mS/μm)

reduced 2:1 ✓

edge capacitances reduced 2:1 ✓

substrate capacitances reduced 2:1 ✓

must reduce ρc 4:1

Slide: Mark Rodwell


“External” Resistances are Critical

• Contact resistance Rc

• Access & spreading resistance

• Interface resistance & source starvation

• Sharvin resistance (quantized conductance):

Source Drain

Dielectric, εr

Gate

Channel (p or NID)

Back Barrier

n+ n+

Lg

tox

xj

Rc

Coverlap

Cox

RaccessRsp & Rif &

Rq

Resistances constant ⇒ Resistivities must scale as 1/Lg2:

Cfringing

6

Csemi ~ εchan.LgW/d


Transconductance Scaling Challenges

Channel

Bottom Barrier

Top Barrier or Oxide

GateCox scales as 1/EOT ...EOT scales poorly

gm ~ (1/Cg-ch)vthWg

☹

☹

☹

Cdos =

E1

E1d

dtqwtqw

CB CBWavefunction pushed away from gateCsemi scales poorly

Thick channel Thin channel

...Smaller

...Smaller

...Should stay constant (double mA/µm)

But voltage divider exists:

Solution: Increase vth using new material.

Similar problem with overlap & fringing capacitances.

7

MOTIVATION FOR REGROWN FETs


Device Choice: Why not HEMTs?

Wide recess→ okay DIBL, subthreshold slope, Cgd

Wide contacts→ Rc okay even with poor contacts

Injection thru barrier

HEMTs obscure scaling issues.

Low gate barrier = Limited carrier densityLong recesses, lightly

doped = high Raccess

Not scaled}


Scalable III-V FET Design

Classic III-V FET (details vary):

ChannelBottom BarrierInAlAs Barrier

Top Barrier or Oxide

Gate

Large Raccess{Low

doping

GapSource Drain

Large Rc {

Large Area Contacts{

• Advantages of III-V’s

• Disadvantages of III-V’s

III-V FET with Self-Aligned Regrowth:

ChannelIn(Ga)P Etch StopInAlAs Barrier

High-k

Gate

n+ Regrowth

High Velocity Channel

Small RaccessSmall

Rc

Self-aligned

High doping: 1013 cm-2 avoids source exhaustion

2D injection avoids source starvation

Low sheet resistance;dopants active as-grown

High mobilityaccess regions

High barrier


Big Picture: Salicide-like Process

High-k

Metal Gate

ChannelSalicide

Salicides

Advantages:Self-alignedNo e- barrier

CMOS-safe metals

Analogy: Self-aligned silicide (salicide) process:

Barrier

Source Contact

High-k

Metal Gate

Channel

n+ Regrowth

Regrown Contacts

....

Break from Silicon:No implantationInsufficient dopingSurface damageAnnealing is no panaceaEncapsulate gate metalsArsenic cappingShip wafers for high-kStrain is cheap

Take from Silicon:Unlike classic III-V devices:Avoid liftoffDry etchesSelf-aligned processesSurface channelsDo III-V fabrication in Si-like fashion.

....

11

III-V Benefits and Challenges


Channel Roughness Scattering

•Challenge: Sixth power (!) scattering from interface roughness:

µ ~ (1/Mscat)2 ~ 1/(∂E/∂W)2 ~ W6 (Gold SSC

1987)

•Trend weaker in shallow or narrow wells (Li SST 2005)

•Screening helps too•Does not seem to be a problem for 5nm InGaAs channels.

Fit: ~W-1.95

JK 84mAμm

Vgs Vth

1V

3/ 2

K n m* /m0 1/2

1 cdos,o / cox m* /m0 1/ 2

Drive Current in the Ballistic & Degenerate Limits

Inclusive of non-parabolic band effects, which increase cdos , InGaAs & InP have near-optimum mass for 0.4-1.0 nm EOT gate dielectrics

eot includes the electron wavefunction depth

Rodwell IPRM 2008

where


High Mobility in Narrow InGaAs Channels

• Unclear whether high mobility is in narrow channel• Unreasonable simulation difficulty.

– Nonparabolic bands, degenerate statistics, bandgap renormalization, screening...

• Need FET to remove uncertainty: eliminate doping altogether.

No Shubnikov-de Haas Oscillations

InAlAs mobility: 346

Hall Measurements

Electrons occupy multiple channels

But electrons aren’t in InAlAs...?

4K

High-k

Metal Gate

InGaAsn+ RegrowthInP or InGaP etch

stopInAlAs barrier

SourceContact

DrainContact

Regrowth Interface Resistances

In-situ Mo Contact ρc < 1 Ω- μm2

InGaAs-InP re-growth resistance = 6 Ω- μm2 (on thick InP).

25 nm regrown InGaAs Rsh=70 Ω/sq

InGaAs-InGaAs re-growth resistance < 1 Ω- μm2.

Interface resistances tested in separate blanket regrowths (no gates):

16

FABRICATION PROCESS FLOW


Process Flow: Gate Deposition

High-k first on pristine channel.

Tall gate stack.

Litho.

Selective etches to channel.

NID InGaAs Channel

InP/InGaP etch stop

InAlAs barrier

InP substrate

Critical etch process:Stop on channel with no damage

SiO2

r

Metals

Cr


Gate Stack: Multiple Layers & Selective Etches

Key: stop etch before reaching dielectric, then gentle low-power etch to stop on dielectric

Rodwell IPRM 2008


Process Flow: Sidewalls & Recess Etch

SiNx or SiO2 sidewallsEncapsulate gate metals

Controlled recess etchSlow facet planesNot needed for depletion-mode FETs

InP/InGaP etch stop

InAlAs barrier

InP substrate

Metals

r

Channel

SiO2,SiNx


Surface Preparation Before Regrowth

UV-ozone (20 min)

HCl:H2O 1:10 etch (60 sec)H2O rinse, N2 dry

Bake under ultrahigh vacuum

Hydrogen cleaning10-6 Torr, 30 min., 400°C (InP) or 420°C (InGaAs)Thermal deoxidation may work also.

rMetal

SiO2, SiNx

O3 (g)

rMetal

SiO2, SiNx

HCl+H2O (l)

r

Metal

SiO2, SiNx

H2 + H (g)

Channel

Channel

Channel


Clean Surface Before Regrowth

Clean, undamaged surface after Al2O3 dielectric etch & InGaAs recess etch.

InP etchstop

22

Mo


At Last: Regrowth & Metal

Regrow n++ InGaAsDoping: n~3.6x1019 cm-3 (Si~8x1019 cm-3)V/III ratio=30Tsub = 460°C

InP etch stop

InAlAs barrier

SiO2,SiNx

Metals

rn++InGaAs

n++InGaA

sChanne

l

Blanket metallization: Either in-situ Mo or ex-situ TiW Singisetti APL, submitted, or Crook APL 2007

RHEED before growth


TEM of Regrowth: InGaAs on InGaAs

InGaAs n+

HRTEM

Interface

HAADF-STEM`

2 nm

Interface

InGaAs n+ regrowth

Regrowth on processed but unpatterned InGaAs.No extended defects.


Polymer

1. Spin on thick polymer

Regrowth InGaAs

Polymer

Regrowth InGaAs

2. Mo & InGaAs Etch

OxideMetal

SiO2

OxideMetal

SiO2

InGaP etch stop

InGaP etch stopInAlAs

barrierInAlAs barrier

Removing Excess Overgrowth

Approach #1:Remove it

Height-selective etchWistey MBE 2008 & Burek JCG 2009

Approach #2:Don’t Grow It

Quasi-Selective growthWistey EMC 2009


Regrowth on InP vs. InGaP

•Conversion of <6nm InP to InAs

•Strain relaxation InAlAs barrier

InGaAs

InP etch stop

InP regrowth SEMInP regrowth RHEED

SEM: U. Singisetti

InAlAs barrier

InGaAs InAsInAsP

As

As


Regrowth on InGaP

2

InGaP regrowth RHEED InGaP regrowth SEM

InAlAs barrier

InGaAs

InGaPInGaP InGaPInGaAs InGaAs

Converted from InGaP

P

As•Replace InP with InGaP

•Converts to InGaAs (good!)

•Strain compensationWistey EMC 2008

27

DEPLETION-MODE MOSFETS


Scalable InGaAs MOSFETs

InGaAs Channel, NID

10 nm InAlAs Setback, NID

Semi-insulating InP Substrate

5 nm Al2O3

50 nm W

300 nm SiO2 Cap

SiN

x

5 nm InAlAs, Si=8x1019 cm-3

200 nm InAlAs buffer

50 nm Cr

n++ regrowth

Mo Mo

n++ regrowth3 nm InGaP Etch Stop, NID

Top view SEM Obliqueview


Scalable InGaAs MOSFETs

InGaAs Channel, NID


Semi-insulating InP Substrate

5 nm Al2O3

50 nm W

300 nm SiO2 Cap

SiN

x


200 nm InAlAs buffer

50 nm Cr

n++ regrowth

Mo Mo


0.5µm0.5µm0.6µm0.7µm0.8µm0.9µm

1µm10µm

•Conservative doping design:•[Si] = 4x1013 cm-2

•Bulk n = 1x1013 cm-2 >> Dit

•Large setback + high doping = Can’t turn off


Series Resistance

InGaAs Channel, NID


5 nm Al2O3

50 nm W

300 nm SiO2 Cap

SiN

x


InAlAs buffer

50 nm Cr

Possible causes:Poly nucleation at gateThinning near gate Strain-induced dislocations Incomplete underfillInsufficient doping under sidewall

Mo


Now known to be a growth issue. See DRC & EMC 2009 for solution.


The Shape of Things to Come

Generalized Self-Aligned Regrowth Designs:

ChannelBack BarrierSubstrate

Top Barrier

Gate

n+ Regrowth

• Self-aligned regrowth can also be used for:

• GaN HEMTs (with Mishra group at UCSB)

• GaAs pMOS FETs

• InGaAs HBTs and HEMTs

• All high speed III-V electronics

Back BarrierSubstrate

Top Barrier

Gate

Recessed Raised

Channel


Conclusions

• Scaled III-V CMOS requires more than reduced dimensions

• InGaAs offers a high velocity channel, high mobility access

• Self-aligned regrowth: a roadmap for scalable III-V FETs

–Provides III-V’s with a salicide equivalent

–Can improve GaN and GaAs FETs too

• DFETs show peak gm = 0.24mS/µm

• High resistance (a growth problem) limited FET performance


Acknowledgements

• Rodwell & Gossard Groups (UCSB): Uttam Singisetti, Greg Burek, Ashish Baraskar, Vibhor Jain...

• McIntyre Group (Stanford): Eunji Kim, Byungha Shin, Paul McIntyre

• Stemmer Group (UCSB): Joël Cagnon, Susanne Stemmer

• Palmstrøm Group (UCSB): Erdem Arkun, Chris Palmstrøm

• SRC/GRC funding

• UCSB Nanofab: Brian Thibeault, NSF


Conclusions

• Scaled III-V CMOS requires more than reduced dimensions

• InGaAs offers a high velocity channel, high mobility access

• Self-aligned regrowth: a roadmap for scalable III-V FETs

–Provides III-V’s with a salicide equivalent

–Can improve GaN and GaAs FETs too

• DFETs show peak gm = 0.24mS/µm

• High resistance (a growth problem) limited FET performance

iii-v/ge channel engineering for future cmos 215th ecs meeting, san francisco, may 28, 2009 mark a....

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