dspic33f flash programming ... -...

dsPIC33FdsPIC33F Flash Programming Specification for

Devices with Volatile Configuration Bits

1.0 DEVICE OVERVIEWThis document defines the programming specificationfor the dsPIC33F 16-bit Digital Signal Controller (DSC)families with volatile Configuration bits. This program-ming specification is required only for those developingprogramming support for the following devices:

• dsPIC33FJ16GP101• dsPIC33FJ16GP102• dsPIC33FJ16MC101• dsPIC33FJ16MC102• dsPIC33FJ06GS001• dsPIC33FJ06GS101A• dsPIC33FJ06GS102A• dsPIC33FJ06GS202A• dsPIC33FJ09GS302

Customers using only one of these devices should usedevelopment tools that already provide support fordevice programming.

Topics covered include:

• Section 1.0 “Device Overview”• Section 2.0 “Programming Overview”• Section 3.0 “Device Programming – ICSP”• Section 4.0 “Device Programming – Enhanced

ICSP”• Section 5.0 “Programming the Programming

Executive to Memory”• Section 6.0 “The Programming Executive”• Section 7.0 “Device ID”• Section 8.0 “Checksum Computation”• Section 9.0 “AC/DC Characteristics and

Timing Requirements”• Appendix A: “Hex File Format”• Appendix B: “Revision History”

2.0 PROGRAMMING OVERVIEWThere are two methods of programming the devicesdiscussed in this programming specification. They are:

• In-Circuit Serial Programming™ (ICSP™) programming capability

• Enhanced In-Circuit Serial Programming

The ICSP programming method is the most directmethod to program the device; however, it is also theslower of the two methods. It provides native, low-levelprogramming capability to erase, program and verifythe chip.

The Enhanced ICSP protocol uses a faster method thattakes advantage of the programming executive, asillustrated in Figure 2-1. The programming executiveprovides all the necessary functionality to erase,program and verify the chip through a small commandset. The command set allows the programmer toprogram a device without having to deal with thelow-level programming protocols of the chip.

FIGURE 2-1: PROGRAMMING SYSTEM OVERVIEW FOR ENHANCED ICSP™

This specification is divided into two major sections thatdescribe the programming methods independently.Section 3.0 “Device Programming – ICSP”describes the ICSP method. Section 4.0 “DeviceProgramming – Enhanced ICSP” describes theEnhanced ICSP method.

dsPIC33F

Programmer ProgrammingExecutive

On-Chip Memory

© 2011 Microchip Technology Inc. DS70659B-page 1

dsPIC33F DEVICES WITH VOLATILE CONFIGURATION BITS

2.1 Required ConnectionsThe dsPIC33F family of devices require specificconnections for programming to take place. Theseconnections include power, VCAP, MCLR, and oneprogramming pair (PGEDx/PGECx). Table 2-1describes these connections (refer to the specificdevice data sheet for pin descriptions and powerconnection requirements).

TABLE 2-1: PINS USED DURING PROGRAMMING

2.2 Program Memory Write/Erase Requirements

The program Flash memory has a specific write/eraserequirement that must be adhered to, for proper deviceoperation. The rule is that any given word in memorymust not be written without first erasing the page inwhich it is located. Thus, the easiest way to conform tothis rule is to write all the data in a programming blockwithin one write cycle. The programming methodsspecified in this document comply with thisrequirement.

Note: Refer to the specific device data sheet forcomplete pin diagrams.

During Programming

Pin Name Pin Type Pin Description

MCLR P Programming EnableVDD and AVDD(1) P Power Supply(1)

VSS and AVSS(1) P Ground(1)

VCAP P CPU Logic Filter Capacitor Connection

PGECx I Programming Pin Pair: Serial Clock

PGEDx I/O Programming Pin Pair: Serial Data

Legend: I = Input O = Output P = PowerNote 1: All power supply and ground pins must be

connected including AVDD and AVSS.

Note: A program memory word can beprogrammed twice before an erase, butonly if (a) the same data is used in bothprogram operations or (b) bits containing‘1’ are set to ‘0’ but no ‘0’ is set to ‘1’.

DS70659B-page 2 © 2011 Microchip Technology Inc.


2.3 Memory MapThe program memory map extends from 0x0 to0xFFFFFE. Code storage is located at the base of thememory map. The last locations of implementedprogram memory are reserved for the deviceConfiguration bits.

Table 2-2 shows the program memory size, the size ofthe erase blocks, and the number of erase blockspresent in each device variant.

Locations 0x800000 through 0x8007FE are reservedfor executive code memory. This region stores theProgramming Executive (PE), which is used for deviceprogramming. This region of memory cannot be usedto store user code.

Locations 0xFF0000 and 0xFF0002 are reserved forthe Device ID Word registers. These bits can be usedby the programmer to identify which device type isbeing programmed. They are described in Section 7.0“Device ID”. The Device ID registers read outnormally, even after code protection is applied.

Figure 2-2 provides a generic memory map for thedevices listed in Table 2-2. See the specific device datasheet for exact memory addresses.

FIGURE 2-2: PROGRAM MEMORY MAP

Use

r Mem

ory

Spac

e

0x000000

Configuration Bytes

Code Memory

0x0XXXXX0x0XXXXX

Con

figur

atio

n M

emor

y Sp

ace

0x800000

Device ID0xFEFFFE0xFF0000

0xFFFFFE

Reserved

Reserved

0x8007FE

Executive Code Memory0x7FFFFE

0xFF00020xFF0004Reserved

(2 x 16-bit)

User Flash

(1024 x 24-bit)0x800800

0x0XXXXX0x0XXXXX

Note: Memory map is for reference only. Refer to the specificdevice data sheet for exact memory addresses.

Configuration Bytes0xFA00020xFA0000

0xF9FFFE

Reserved

TABLE 2-2: CODE MEMORY SIZE

dsPIC33F DeviceUser Memory Address Limit

(Instruction Words)

Erase Page Size (Instruction Words)

Erase Blocks (Pages)

Executive Memory Address Limit

(Instruction Words)

dsPIC33FJ16GP101 0x002BFA (5.6K) 512 12 0x8007FE (1K)dsPIC33FJ16GP102 0x002BFA (5.6K) 512 12 0x8007FE (1K)dsPIC33FJ16MC101 0x002BFA (5.6K) 512 12 0x8007FE (1K)dsPIC33FJ16MC102 0x002BFA (5.6K) 512 12 0x8007FE (1K)dsPIC33FJ06GS001 0x00FEE (2K) 512 4 0x8007FE (1K)dsPIC33FJ06GS101A 0x00FEE (2K) 512 4 0x8007FE (1K)dsPIC33FJ06GS102A 0x00FEE (2K) 512 4 0x8007FE (1K)dsPIC33FJ06GS202A 0x00FEE (2K) 512 4 0x8007FE (1K)dsPIC33FJ09GS302 0x017EE (3K) 512 6 0x8007FE (1K)dsPIC33FJ16GP101 0x002BFA (5.6K) 512 12 0x8007FE (1K)



2.4 Configuration Bits2.4.1 OVERVIEWThe dsPIC33F devices have Configuration bits storedin the last locations of implemented program memory.These bits can be set or cleared to select variousdevice configurations. There are two types ofConfiguration bits: system operation bits, andcode-protect bits. The system operation bits determinethe power-on settings for system level components,such as the Oscillator and the Watchdog Timer. Thecode-protect bits prevent program memory from beingread and written.

Table 2-3 lists the address and location of theConfiguration bits for dsPIC33FJ16GP/MC10Xdevices.Table 2-4 lists the address and locations of theConfiguration bits for dsPIC33FJ06GS001,dsPIC33FJ06GSX0XA, and dsPIC33FJ09GS302devices.

TABLE 2-3: dsPIC33FJ16GP/MC10X CONFIGURATION BITS

TABLE 2-4: dsPIC33FJ06GS001, dsPIC33FJ06GSX0XA, AND dsPIC33FJ09GS302 CONFIGURATION BITS

File Name Addr. Bit Range Bit 23/15/7 Bit 22/14/6 Bit 21/13/5 Bit 20/12/4 Bit 19/11/3 Bit 18/10/2 Bit 17/9/1 Bit 16/8/0

CONFIG2 002BFC 23:16 — — — — — — — —

15:8 IESO PWMLOCK(2) PWMPIN(2) WDTWIN<1:0> FNOSC<2:0>7:0 FCKSM<1:0> OSCIOFNC IOL1WAY LPOL(2) ALTI2C1 POSCMD<1:0>

CONFIG1 002BFE 23:16 — — — — — — — —

15:8 Reserved(3) Reserved(3) GCP GWRP Reserved(4) HPOL(2) ICS<1:0>7:0 FWDTEN WINDIS PLLKEN WDTPRE WDTPOST<3:0>

Legend: — = unimplemented, read as ‘1’.Note 1: During a Power-on Reset (POR), the contents of these Flash locations are transferred to the Configuration Shadow

registers.2: This bit is reserved on dsPIC33FJ16GP101/102 devices and reads as ‘1’.3: This bit is reserved; program as ‘0’.4: This bit is reserved for use by development tools and must be programmed as ‘1’.

File Name Addr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

FICD000FF0(1)

Reserved(3) — — Reserved(4) — — ICS<1:0>0017F0(2)

Reserved000FF2(1)

— — — — — — — —0017F2(2)

FWDT000FF4(1)

FWDTEN — PLLKEN WDTPRE WDTPOST<3:0>0017F4(2)

FOSC000FF6(1)

FCKSM<1:0> IOL1WAY — — OSCIOFNC POSCMD<1:0>0017F6(2)

FOSCSEL000FF8(1)

IESO — — — — FNOSC<2:0>001F78(2)

FGS000FFA(1)

— — — — — — GCP GWRP0017FA(2)

Reserved000FFC(1)

— — — — — — — —0017FC(2)

Reserved000FFE(1)

— — — — — — — —0017FE(2)

Legend: — = unimplemented, read as ‘1’.Note 1: This address applies to dsPIC33FJ06GS001 and dsPIC33FJ06GSX0XA Configuration bits.

2: This address applies to dsPIC33FJ09GS302 Configuration bits.3: This bit is reserved for use by development tools and must be programmed as ‘1’.4: This bit is reserved; program as ‘0’.



2.4.2 CODE-PROTECT CONFIGURATION BITS

The Configuration bits control the code protectionfeatures, with two forms of code protection beingprovided. One form prevents code memory from beingwritten (write protection) and the other prevents codememory from being read (i.e., read protection).

The GWRP bit (CONFIG1<12>) controls write protec-tion and the GCP bit (CONFIG1<13>) controls readprotection. Protection is enabled when the respectivebit is ‘0’.

Erasing sets GWRP and GCP to ‘1’, which allows thedevice to be programmed.

When write protection is enabled (GWRP = 0), anyprogramming operation to code memory will fail.

When read protection is enabled (GCP = 0), any readfrom code memory will cause a 0x0 to be read, regard-less of the actual contents of code memory. Since theprogramming executive always verifies what it pro-grams, attempting to program code memory with readprotection enabled also will result in failure.

It is imperative that both GWRP and GCP are ‘1’ whilethe device is being programmed and verified. Only afterthe device is programmed and verified should eitherGWRP or GCP be programmed to ‘0’ (see Section 2.4“Configuration Bits”).

Note 1: Bulk Erasing the program memory is theonly way to reprogram code-protect bitsfrom an ON state (‘0’) to an OFF state(‘1’).

2: Performing a page erase operation onthe last page of program memory clearsthe Flash Configuration words, enablingcode protection as a result. Therefore,users should avoid performing pageerase operations on the last page ofprogram memory.

3: If the General Segment Code-Protect bit(GCP) is programmed to ‘0’, code mem-ory is code-protected and can not beread. Code memory must be read andverified before enabling read protection.See Section 2.4.2 “Code-Protect Con-figuration Bits” for detailed informationabout code-protect Configuration bits,and Section 3.10 “Verify Code Memoryand Configuration Bits” for detailsabout reading and verifying codememory and Configuration Words andBytes



3.0 DEVICE PROGRAMMING – ICSP

ICSP mode is a special programming protocol thatallows you to read and write to dsPIC33F device familymemory. The ICSP mode is the most direct methodused to program the device, which is accomplished byapplying control codes and instructions serially to thedevice using the PGECx and PGEDx pins. ICSP modealso has the ability to read executive memory to deter-mine if the programming executive is present and towrite the programming executive to executive memoryif Enhanced ICSP (E-ICSP) mode will be used.

In ICSP mode, the system clock is taken from thePGECx pin, regardless of the device’s oscillator Con-figuration bits. All instructions are shifted serially into aninternal buffer, then loaded into the instruction registerand executed. No program fetching occurs from inter-nal memory. Instructions are fed in 24 bits at a time.PGEDx is used to shift data in, and PGECx is used asboth the serial shift clock and the CPU execution clock.

3.1 Overview of the Programming Process

Figure 3-1 illustrates the high-level overview of theprogramming process. After entering ICSP mode, thefirst action is to Bulk Erase program memory. Next, thecode memory is programmed, followed by the deviceConfiguration words. Code memory (including theConfiguration words) is then verified to ensure that pro-gramming was successful. Then, program thecode-protect Configuration bits, if required.

FIGURE 3-1: HIGH-LEVEL ICSP™ PROGRAMMING FLOW

Note 1: During ICSP operation, the operatingfrequency of PGECx must not exceed5 MHz.

2: ICSP mode is slower then EnhancedICSP mode for programming.

Start

Perform BulkErase

Program Memory

Verify Program Memory

End

Enter ICSP™

Program Code-protect

Exit ICSP

andConfiguration Words

and Configuration Words

Configuration Bits



3.2 Entering ICSP ModeAs illustrated in Figure 3-2, entering ICSP Program/Verify mode requires three steps:1. MCLR is briefly driven high then low (P21)(1).2. A 32-bit key sequence is clocked into PGEDx.3. MCLR is then driven high within a specified

period of time ‘P19’ and held.

The programming voltage applied to MCLR is VIH,which is essentially VDD in the case of dsPIC33Fdevices. There is no minimum time requirement forholding at VIH. After VIH is removed, an interval of atleast P18 must elapse before presenting the keysequence on PGEDx.

The key sequence is a specific 32-bit pattern,‘0100 1101 0100 0011 0100 1000 0101 0001’(more easily remembered as 0x4D434851 inhexadecimal). The device will enter Program/Verifymode only if the sequence is valid. The Most Significantbit of the most significant nibble must be shifted in first. Once the key sequence is complete, VIH must beapplied to MCLR and held at that level for as long asProgram/Verify mode is to be maintained. An interval ofat least time P19, and P1 * 5, must elapse before pre-senting data on PGEDx. Signals appearing on PGEDxbefore this time has elapsed will not be interpreted asvalid.On successful entry, the program memory can beaccessed and programmed in serial fashion. While inICSP mode, all unused I/Os are placed in thehigh-impedance state.

FIGURE 3-2: ENTERING ICSP™ MODE

Note 1: If a capacitor is present on the MCLR pin,the high time for entering ICSP mode canvary.

MCLR

PGEDx

PGECx

VDD

P6P14

b31 b30 b29 b28 b27 b2 b1 b0b3...

Program/Verify Entry Code = 0x4D434851

P1AP1B

P18

P19

0 1 0 0 1 0 0 0 1

P7VIH VIH

P21 P1 · 5



3.3 ICSP OperationAfter entering into ICSP mode, the CPU is Idle.Execution of the CPU is governed by an internal statemachine. A 4-bit control code is clocked in using PGECxand PGEDx and this control code is used to commandthe CPU (see Table 3-1).

The SIX control code is used to send instructions to theCPU for execution and the REGOUT control code isused to read data out of the device via the VISI register.

TABLE 3-1: CPU CONTROL CODES IN ICSP™ MODE

3.3.1 SIX SERIAL INSTRUCTION EXECUTION

The SIX control code allows execution of assemblyinstructions. When the SIX code is received, the CPU issuspended for 24 clock cycles, as the instruction is thenclocked into the internal buffer. Once the instruction isshifted in, the state machine allows it to be executed overthe next four clock cycles. While the received instructionis executed, the state machine simultaneously shifts inthe next 4-bit command (see Figure 3-3).

FIGURE 3-3: SIX SERIAL EXECUTION

FIGURE 3-4: PROGRAM ENTRY AFTER RESET

4-bit Control Code Mnemonic Description

0000b SIX Shift in 24-bit instruction and execute.

0001b REGOUT Shift out the VISIregister.

0010b-1111b N/A Reserved.

Note 1: Coming out of the ICSP entry sequence,the first 4-bit control code is alwaysforced to SIX and a forced NOP instruc-tion is executed by the CPU. Five addi-tional PGECx clocks are needed onstart-up, thereby resulting in a 9-bit SIXcommand instead of the normal 4-bit SIXcommand. After the forced SIX isclocked in, ICSP operation resumes asnormal (the next 24 clock cycles load thefirst instruction word to the CPU). SeeFigure 3-4 for details.

P4

1 2 3 23 24 1 2 3 4P1

PGECxP4a

PGEDx

24-bit Instruction Fetch Execute 24-bit Instruction,Execute PC – 1,Fetch SIX Control Code Fetch Next Control Code

4 5 6 7 8 18 19 20 21 2217

LSB X X X X X X X X X X X X X X MSB

PGEDx = Input

P2

P3P1B

P1A

1 2

0 0 0 00 0

3 4

0 0

P4

2 3 1 2 3 23 24 1 2 3 4P1

PGECxP4a

PGEDx

24-bit Instruction Fetch Execute 24-bit Instruction,Execute PC – 1,

1 4

0 0 0 0

Fetch SIX Control Code Fetch Next Control Code

4 5 6 7 8 18 19 20 21 2217

LSB X X X X X X X X X X X X X X MSB

PGEDx = Input

P2

P3P1B

P1A

5 6 7

0 0 0 00 0 0

8 9

0 0



3.3.2 REGOUT SERIAL INSTRUCTION EXECUTION

The REGOUT control code allows for data to be extractedfrom the device in ICSP mode. It is used to clock the con-tents of the VISI register out of the device over thePGEDx pin. After the REGOUT control code is received,the CPU is held Idle for eight cycles. After these eightcycles, an additional 16 cycles are required to clock thedata out (see Figure 3-5).

The REGOUT code is unique because the PGEDx pin isan input when the control code is transmitted to thedevice. However, after the control code is processed,the PGEDx pin becomes an output as the VISI registeris shifted out.

FIGURE 3-5: REGOUT SERIAL EXECUTION

Note: The device will latch input PGEDx data onthe rising edge of PGECx and will outputdata on the PGEDx line on the rising edgeof PGECx. For all data transmissions, theLeast Significant bit (LSb) is transmittedfirst.

1 2 3 4 1 2 7 8PGECx

P4

PGEDx

PGEDx = Input

Execute Previous Instruction, CPU Held in Idle Shift Out VISI Register<15:0>

P5

PGEDx = Output

1 2 3 1 2 3 4

P4a

11 13 15 161412

No Execution Takes Place,Fetch Next Control Code

0 0 0 0 0

PGEDx = Input

MSb1 2 3 41

4 5 6

LSb 141312... 11100

Fetch REGOUT Control Code

0



3.4 Flash Memory Programming in ICSP Mode

3.4.1 PROGRAMMING OPERATIONSFlash memory write and erase operations arecontrolled by the NVMCON register. Programming isperformed by setting NVMCON to select the type oferase operation (Table 3-2) or write operation(Table 3-3) and initiating the programming by settingthe WR control bit (NVMCON<15>). In ICSP mode, all programming operations areself-timed. There is an internal delay between the usersetting the WR control bit and the automatic clearing ofthe WR control bit when the programming operation iscomplete. Please refer to Section 9.0 “AC/DC Char-acteristics and Timing Requirements” for detailedinformation about the delays associated with variousprogramming operations.

TABLE 3-2: NVMCON ERASE OPERATIONS

TABLE 3-3: NVMCON WRITE OPERATIONS

3.4.2 STARTING AND STOPPING A PROGRAMMING CYCLE

The WR bit (NVMCON<15>) is used to start an eraseor write cycle. Setting the WR bit initiates theprogramming cycle.All erase and write cycles are self-timed. The WR bitshould be polled to determine if the erase or write cyclehas been completed. Starting a programming cycle isperformed as follows:

BSET NVMCON, #WR

NVMCONValue Erase Operation

0x404F Erase code memory or executive memory (does not erase Device ID registers)

0x404D Erase General Segment memory

0x4042 Erase a page of program memory

NVMCONValue Write Operation

0x4003 Program a code memory word



REGISTER 3-1: NVMCON: FLASH MEMORY CONTROL REGISTER

R/SO-0(1) R/W-0(1) R/W-0(1) U-0 U-0 U-0 U-0 U-0WR WREN WRERR — — — — —

bit 15 bit 8

U-0 R/W-0(1) U-0 U-0 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1)

— ERASE — — NVMOP<3:0>bit 7 bit 0

Legend: SO = Satiable only bitR = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 WR: Write Control bit1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is

cleared by hardware once operation is complete0 = Program or erase operation is complete and inactive

bit 14 WREN: Write Enable bit1 = Enable Flash program/erase operations0 = Inhibit Flash program/erase operations

bit 13 WRERR: Write Sequence Error Flag bit1 = An improper program or erase sequence attempt or termination has occurred (bit is set

automatically on any set attempt of the WR bit)0 = The program or erase operation completed normally

bit 12-7 Unimplemented: Read as ‘0’bit 6 ERASE: Erase/Program Enable bit

1 = Perform the erase operation specified by NVMOP<3:0> on the next WR command0 = Perform the program operation specified by NVMOP<3:0> on the next WR command

bit 5-4 Unimplemented: Read as ‘0’bit 3-0 NVMOP<3:0>: NVM Operation Select bits(2)

If ERASE = 1:1111 = Memory bulk erase(3)

1101 = Erase General Segment0010 = Program Memory page erase

If ERASE = 0:0011 = Memory word program

Note 1: These bits can only be reset on a Power-on Reset (POR).2: All other combinations of NVMOP<3:0> are unimplemented.3: This command will erase either all of program memory or all of executive memory, but not both.



3.5 Erasing Program MemoryThe procedure for erasing program memory (includingcode-protect bits) is shown in Figure 3-6. It consists ofsetting NVMCON to 0x404F, initializing the TBLPAGregister to 0x00, and then executing the programmingcycle. For page erase operations, the NVMCON valueshould be modified suitably, according to Table 3-2.

Table 3-4 illustrates the ICSP programming process forErasing program memory.

FIGURE 3-6: PROGRAM MEMORY ERASE FLOW

TABLE 3-4: SERIAL INSTRUCTION EXECUTION FOR ERASING PROGRAM MEMORY

Start

End

Set the WR bit to Initiate Erase

Write 0x404F to NVMCON SFR

Delay P11 + P10 Time

Initialize the TBLPAG register to 0x00

4-bit Control Code

Data(Hex) Description

Step 1: Exit the Reset vector.000000000000

040200040200000000

GOTO 0x200GOTO 0x200NOP

Step 2: Set the NVMCON to erase all program memory.00000000

2404FA883B0A

MOV #0x404F, W10MOV W10, NVMCON

Step 3: Initiate the TBLPAG register for program memory.00000000

200001880191

MOV #0x00, W1MOV W1, TBLPAG

Step 4: Initiate the erase cycle.00000000000000000000

A8E761000000000000000000000000

BSET NVMCON, #WR NOPNOPNOPNOP

Step 5: Wait for Bulk Erase operation to complete to ensure that the WR bit is clear.— — Externally time ‘P11’ + ‘P10’ ms (see Section 9.0 “AC/DC Characteristics and

Timing Requirements”) to allow sufficient time for the Bulk Erase operation to complete.



3.6 Writing Code MemoryFigure 3-7 provides a high level description of how towrite to code memory. First, the device is configured forwrites, one instruction word is loaded into the writelatch, and the write point is incremented. Next, the writesequence is initiated, and finally, the WR bit is checkedfor the sequence to be complete. This processcontinues for all words to be programmed.

Table 3-5 describes the ICSP programming process forwriting program memory.

FIGURE 3-7: PROGRAM CODE MEMORY FLOW

Start Write Sequence

Alllocations

done?

No

End

Start

Yes

and Poll for WR bitto be cleared

ConfigureDevice for

Writes

Load Lower Word and Upper Byte of instruction

to Write Latch and increment the Write Pointer

TABLE 3-5: SERIAL INSTRUCTION EXECUTION FOR WRITING CODE MEMORY4-bit Control

CodeData (Hex) Description


040200040200000000


Step 2: Set the NVMCON register to program one program memory word.000000000000

240030000000883B00

MOV #0x4003, W0NOPMOV W0, NVMCON

Step 3: Initialize the TBLPAG register to the first page of program memory.000000000000

200001000000880191

MOV #0x00, W1NOPMOV W1, TBLPAG

Step 4: Initialize the write pointer (W2) for the TBLWT instruction.0000 2xxxx2 MOV #<DestinationAddress15:0>, W2

Step 5: Load the lower instruction word to the W5 register and the upper instruction byte to the W6 register.00000000

2xxxx5200xx6

MOV #<LOW_WORD>, W5MOV #<HIGH_BYTE>, W6



Step 6: Write the program memory low word and the program memory upper byte into the write latch and incrementthe write pointer.

00000000000000000000000000000000

000000BB0905000000000000BB9906000000000000000000

NOPTBLWTL W5, [W2]NOPNOPTBLWTH.B W6, [W2++]NOPNOPNOP

Step 7: Initiate the write cycle.00000000000000000000

A8E761000000000000000000000000

BSET NVMCON, #WRNOPNOPNOPNOP

Step 8: Wait for the word write operation to complete and make sure WR bit is clear.—

0000000000000001

00000000

—

—

803B00883C20000000<VISI>

040200000000

—

Externally time ‘P13’ ms (see Section 9.0 “AC/DC Characteristics and Timing Requirements”) to allow sufficient time for the Configuration word write operation to complete.

MOV NVMCON, W0MOV W0, VISINOPClock out contents of VISI register.

GOTO 0x200NOP

Repeat until the WR bit is clear.Step 9: Repeat steps 5-8 to write the remaining program words.

TABLE 3-5: SERIAL INSTRUCTION EXECUTION FOR WRITING CODE MEMORY (CONTINUED)4-bit Control




3.7 Writing Configuration WordsThe procedure for writing Configuration bits is similar tothe procedure for writing code memory, except that16-bit data words are written (with the upper bytes readbeing all ‘0’s) instead of 24-bit words. Since there aremultiple Configuration words or bytes, they are writtenone word or byte at a time.

To change the values of the Configuration bits oncethey have been programmed, the device must be ChipErased, as described in Section 3.5 “Erasing Pro-gram Memory”, and reprogrammed to the desiredvalue. It is not possible to program a ‘0’ to ‘1’, but theymay be programmed from a ‘1’ to ‘0’ to enable codeprotection.

Table 3-6 shows the ICSP programming details forwriting the Configuration bits.

In order to verify the data by reading the Configurationbits after performing the write, the code protection bitsshould initially be programmed to a ‘1’ to ensure thatthe verification can be performed properly. After verifi-cation is finished, the code protection bit can be pro-grammed to a ‘0’ by using a word write to theappropriate Configuration Word.

TABLE 3-6: SERIAL INSTRUCTION EXECUTION FOR WRITING CONFIGURATION BITS

4-bit Control Code



040200040200000000


Step 2: Set the NVMCON register to program one Configuration word.00000000

24003A883B0A

MOV #0x4003, W10MOV W10, NVMCON

Step 3: Initialize the TBLPAG register to the first page of program memory.00000000

200xx0880190

MOV <Address7:0>, W0MOV W0, TBLPAG

Step 4: Initialize the write pointer (W7) for the TBLWT instruction.0000 2xxxx7 MOV <Address15:0>, W7

Step 5: Load the Configuration word data to W6.0000 2xxxx6 MOV #<VALUE>, W6

Step 6: Write the Configuration word data to the write latch and increment the write pointer.00000000000000000000

000000BB1B860000000000000000

NOPTBLWTL W6, [W7++]NOPNOPNOP

Step 7: Initiate the write cycle.00000000000000000000

A8E761000000000000000000000000




Step 8: Wait for the Configuration word write operation to complete and make sure WR bit is clear.—

0000000000000001

00000000

—

—

803B00883C20000000<VISI>

040200000000

—



GOTO 0x200NOP

Repeat until the WR bit is clear.Step 9: Repeat steps 5-8 to write the remaining Configuration bits.

TABLE 3-6: SERIAL INSTRUCTION EXECUTION FOR WRITING CONFIGURATION BITS (CONTINUED)

4-bit Control Code




3.8 Reading Code MemoryReading from code memory is performed by executinga series of TBLRD instructions and clocking out the datausing the REGOUT command.

Table 3-7 shows the ICSP programming details forreading code memory.

To minimize programming time, the same packed dataformat that the programming executive uses is utilized.

See Section 6.2 “Programming ExecutiveCommands” for more details on the packed dataformat.

TABLE 3-7: SERIAL INSTRUCTION EXECUTION FOR READING CODE MEMORY4-bit Control

CodeData(Hex) Description


040200040200000000


Step 2: Initialize TBLPAG and the read pointer (W6) for TBLRD instruction.000000000000

2000008801902xxxx6

MOV <Address7:0>, W0MOV W0, TBLPAGMOV #<Address15:0>, W6

Step 3: Initialize the write pointer (W7) and store the next four locations of code memory to W0:W5.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000

EB0380BA1B96000000000000BADBB6000000000000BADBD6000000000000BA1BB6000000000000BA1B96000000000000BADBB6000000000000BADBD6000000000000BA1BB6000000000000

CLR W7 TBLRDL [W6], [W7++] NOPNOPTBLRDH.B [W6++], [W7++] NOPNOPTBLRDH.B [++W6], [W7++] NOPNOPTBLRDL [W6++], [W7++] NOPNOPTBLRDL [W6], [W7++] NOPNOPTBLRDH.B [W6++], [W7++] NOPNOPTBLRDH.B [++W6], [W7++] NOPNOPTBLRDL [W6++], [W7++] NOPNOP



Step 4: Output W0:W5 using the VISI register and REGOUT command.000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000

883C20000000<VISI>000000883C21000000<VISI>000000883C22000000<VISI>000000883C23000000<VISI>000000883C24000000<VISI>000000883C25000000<VISI>000000

MOV W0, VISI NOPClock out contents of VISI register.NOPMOV W1, VISI NOPClock out contents of VISI register.NOPMOV W2, VISI NOPClock out contents of VISI register.NOPMOV W3, VISI NOPClock out contents of VISI register.NOPMOV W4, VISI NOPClock out contents of VISI register.NOPMOV W5, VISI NOPClock out contents of VISI register.NOP

Step 5: Reset device internal PC.00000000

040200000000

GOTO 0x200 NOP

Step 6: Repeat step 3-5 until all desired code memory is read.

TABLE 3-7: SERIAL INSTRUCTION EXECUTION FOR READING CODE MEMORY (CONTINUED)4-bit Control




3.9 Reading Configuration BitsThe procedure for reading Configuration bits is similarto the procedure for reading code memory, except that16-bit data words are read instead of 24-bit instruc-tions. Since there are multiple Configuration bits, theyare read one word at a time.

Table 3-8 shows the ICSP programming details forreading the Configuration bits.

TABLE 3-8: SERIAL INSTRUCTION EXECUTION FOR READING ALL CONFIGURATION BITS4-bit Control



040200040200000000


Step 2: Initialize TBLPAG, the read pointer (W6) and the write pointer (W7) for TBLRD instruction.00000000000000000000

2000008801902xxxx6EB0380000000

MOV <Address7:0>, W0MOV W0, TBLPAGMOV <Address15:0>, W6CLR W7NOP

Step 3: Read the Configuration word, write it to the VISI register, and clock out the VISI register using the REGOUT command.

0000000000000000000000010000

BA0036000000000000883C20000000<VISI>000000

TBLRDL [W6++], W0 NOP NOPMOV W0, VISINOPClock out contents of VISI register.NOP


040200000000

GOTO 0x200 NOP

Step 5: Repeat step 3-4 to read remaining Configuration bits.



3.10 Verify Code Memory and Configuration Bits

The verify step involves reading back the code memoryspace and comparing it against the copy held in theprogrammer’s buffer. The Configuration words areverified with the rest of the code.

The verify process is illustrated in Figure 3-8. The lowerword of the instruction is read, and then the lower byteof the upper word is read and compared against theinstruction stored in the programmer’s buffer. Refer toSection 3.8 “Reading Code Memory” forimplementation details of reading code memory.

FIGURE 3-8: VERIFY CODE MEMORY FLOW

3.11 Exiting ICSP ModeExiting Program/Verify mode is done by removing VIHfrom MCLR, as illustrated in Figure 3-9. The onlyrequirement for exit is that an interval P16 shouldelapse between the last clock and program signals onPGECx and PGEDx before removing VIH.

FIGURE 3-9: EXITING ICSP™ MODE

Note: Because the Configuration bytes includethe device code protection bit, code mem-ory should be verified immediately afterwriting, if the code protection is to beenabled. This is because the device willnot be readable or verifiable if a deviceReset occurs after the code-protect bithas been cleared.

Read Low Word

Read High Byte

Data?

Allcode memory

verified?

No

Yes

No

Set TBLPTR = 0

Start

Yes

End

with Post-Increment

with Post-Increment

FailureReport Error

DoesInstruction Word

= Expected

MCLR

P16

PGEDx

PGEDx = Input

PGECx

VDD

VIH

VIH

P17



4.0 DEVICE PROGRAMMING – ENHANCED ICSP

This section discusses programming the devicethrough Enhanced ICSP and the programmingexecutive. The programming executive resides inexecutive memory (separate from code memory) and isexecuted when Enhanced ICSP Programming mode isentered. The programming executive provides themechanism for the programmer (host device) toprogram and verify the dsPIC33F devices using asimple command set and communication protocol.There are several basic functions provided by theprogramming executive:

• Read Memory• Erase Memory• Program Memory• Blank Check

The programming executive performs the low-leveltasks required for erasing, programming and verifyinga device. This allows the programmer to program thedevice by issuing the appropriate commands and data.A detailed description for each command is provided inSection 6.2 “Programming Executive Commands”.

4.1 Overview of the Programming Process

Figure 4-1 shows the high-level overview of the pro-gramming process. First, it must be determined if theprogramming executive is present in executive mem-ory, and then Enhanced ICSP mode is entered. Theprogram memory is then erased, and the programmemory and Configuration words are programmed andverified. Last, the code-protect Configuration bits areprogrammed (if required) and Enhanced ICSP mode isexited.

FIGURE 4-1: HIGH-LEVEL ENHANCED ICSP™ PROGRAMMING FLOW

Note: The programming executive uses thedevice’s data RAM for variable storageand program execution. After runningthe programming executive, noassumptions should be made about thecontents of data RAM.

Start

End

Program Memory

Verify Program Memory

Erase

Program Code-protect

Exit Enhanced ICSP

Confirm Presence of

Enter Enhanced


Configuration Bits

Programming Executive

ICSP mode

Program Memory




4.2 Confirming the Presence of the Programming Executive

Before programming, the programmer must confirmthat the programming executive is stored in executivememory. The procedure for this task is illustrated inFigure 4-2.

First, ICSP mode is entered. Then, the uniqueApplication ID Word stored in executive memory is read.If the programming executive is resident, the correctApplication ID Word is read and programming canresume as normal. However, if the Application ID Word isnot present, the programming executive must beprogrammed to executive code memory using themethod described in Section 5.0 “Programming theProgramming Executive to Memory”. See Table 7-1for the Application ID of each device.

Section 3.0 “Device Programming – ICSP” describesthe ICSP programming method. Section 4.3 “Readingthe Application ID Word” describes the procedure forreading the Application ID Word in ICSP mode.

FIGURE 4-2: CONFIRMING PRESENCE OF PROGRAMMING EXECUTIVE

Is

Start

Enter ICSP™ Mode

Application IDpresent?(1)

Yes

No

Application IDCheck the

be ProgrammedProg. Executive must

by reading Address0x8007F0

End

Exit ICSP Mode

Enter Enhanced

Sanity Check

Note 1: See TABLE 7-1: “Device IDs and Revision”for the Application ID of each device.

ICSP Mode



4.3 Reading the Application ID WordThe Application ID Word is stored at address 0x8007F0in executive code memory. To read this memorylocation, you must use the SIX control code to movethis program memory location to the VISI register.Then, the REGOUT control code must be used to clockthe contents of the VISI register out of the device. Thecorresponding control and instruction codes that mustbe serially transmitted to the device to perform thisoperation are shown in Table 3-8.

After the programmer has clocked out the ApplicationID Word, it must be inspected. If the application ID hasthe value listed in TABLE 7-1: “Device IDs and Revi-sion”, the programming executive is resident in mem-ory and the device can be programmed using themechanism described in Section 4.0 “Device Pro-gramming – Enhanced ICSP”. However, if the appli-cation ID has any other value, the programmingexecutive is not resident in memory; it must be loadedto memory before the device can be programmed. Theprocedure for loading the programming executive tomemory is described in Section 5.0 “Programmingthe Programming Executive to Memory”.

TABLE 4-1: SERIAL INSTRUCTION EXECUTION FOR READING THE APPLICATION ID WORD4-bit Control



040200040200000000



200800880190207F00207841000000BA0890000000000000

MOV #0x80, W0 MOV W0, TBLPAGMOV #0x7FO, W0 MOV #VISI, W1 NOP TBLRDL [W0], [W1] NOPNOP

Step 3: Output the VISI register using the REGOUT command.0001 <VISI> Clock out contents of the VISI register.



4.4 Entering Enhanced ICSP ModeAs illustrated in Figure 4-3, entering Enhanced ICSP Program/Verify mode requires three steps:

1. The MCLR pin is briefly driven high then low.2. A 32-bit key sequence is clocked into PGEDx.3. MCLR is then driven high within a specified

period of time and held.

The programming voltage applied to MCLR is VIH,which is essentially VDD in dsPIC33F devices. There isno minimum time requirement for holding at VIH. AfterVIH is removed, an interval of at least P18 must elapsebefore presenting the key sequence on PGEDx.

The key sequence is a specific 32-bit pattern,‘0100 1101 0100 0011 0100 1000 0101 0000’(more easily remembered as 0x4D434850 in hexa-decimal format). The device will enter Program/Verifymode only if the key sequence is valid. The MostSignificant bit (MSb) of the most significant nibble mustbe shifted in first.

Once the key sequence is complete, VIH must beapplied to MCLR and held at that level for as long asProgram/Verify mode is to be maintained. An intervaltime of at least P19, and P1 * 5, must elapse beforepresenting data on PGEDx. Signals appearing onPGEDx before this time has elapsed will not beinterpreted as valid.

On successful entry, the program memory can beaccessed and programmed in serial fashion. While inthe Program/Verify mode, all unused I/Os are placed inthe high-impedance state.

4.5 Blank CheckThe term “Blank Check” implies verifying that thedevice has been successfully erased and has noprogrammed memory locations. A blank or erasedmemory location is always read as ‘1’.

The Device ID registers (0xFF0000:0xFF0002) can beignored by the Blank Check since this region storesdevice information that cannot be erased. Additionally,all unimplemented memory space should be ignoredfrom the Blank Check.

The QBLANK command is used for the Blank Check. Itdetermines if the code memory is erased by testingthese memory regions. A ‘BLANK’ or ‘NOT BLANK’response is returned. If it is determined that the deviceis not blank, it must be erased before attempting toprogram the chip.

FIGURE 4-3: ENTERING ENHANCED ICSP™ MODE

MCLR

PGEDx

PGECx

VDD

P6P14

b31 b30 b29 b28 b27 b2 b1 b0b3...

Program/Verify Entry Code = 0x4D434850

P1AP1B

P18

P19

0 1 0 0 1 0 0 0 0

P7VIH VIH

P21 P1 · 5



4.6 Code Memory Programming4.6.1 PROGRAMMING METHODOLOGYThere are two commands that can used for program-ming code memory when utilizing the ProgrammingExecutive: PROGW and PROGP. The PROGW commandprograms and verifies a single 24-bit instruction wordinto the specified program memory address. The sec-ond and faster command, PROGP, allows up to 64 24-bitinstruction words to be programmed and verified intoprogram memory starting at the specified address. SeeSection 6.0 “The Programming Executive” for a fulldescription for each of these commands.Figure 4-4 and Figure 4-5 illustrate the programmingmethodology for both of these commands. In bothcases, 5.6K instruction words of the dsPIC33FJ16MC/GP10X devices are programmed.

FIGURE 4-4: FLOWCHART FOR SINGLE WORD PROGRAMMING

FIGURE 4-5: FLOWCHART FOR MULTIPLE WORD PROGRAMMING

Note: If a bootloader needs to be programmed,the bootloader code must not be pro-grammed into the first page of code mem-ory. For example, if a bootloader locatedat address 0x200 attempts to erase thefirst page, it would inadvertently eraseitself. Instead, program the bootloader intothe second page (e.g., 0x400).

BaseAddress = 0x0RemainingCmds = 5630

Start

FailureReport Error

End

Yes

No

RemainingCmds =RemainingCmds – 1

Yes

PASS?

No

BaseAddressCommand to Program

Send PROGW

RemainingCmdsIs

‘0’?

BaseAddress + 0x02BaseAddress =

PROGW responseIs

BaseAddress = 0x0RemainingCmds = 87

Start

FailureReport Error

End

Yes

No

RemainingCmds =RemainingCmds – 1

Yes

PASS?

No

BaseAddressCommand to Program

Send PROGW

RemainingCmdsIs

‘0’?

BaseAddress + 0x80BaseAddress =

PROGP responseIs



4.7 Configuration Bit ProgrammingConfiguration bits are programmed one at a time usingthe PROGW command. This command specifies theconfiguration data and address. When Configurationbits are programmed, any unimplemented bits must beprogrammed with a ‘1’.

Multiple PROGW commands are required to program allConfiguration bits. A flowchart for Configuration bitprogramming is shown in Figure 4-6.

FIGURE 4-6: CONFIGURATION BIT PROGRAMMING FLOW

4.8 Programming VerificationAfter code memory is programmed, the contents ofmemory can be verified to ensure that programmingwas successful. Verification requires code memory tobe read back and compared against the copy held inthe programmer’s buffer.

The READP command can be used to read back all theprogrammed code memory and Configuration words.

Alternatively, you can have the programmer performthe verification after the entire device is programmed,using a checksum computation.

See Section 8.0 “Checksum Computation” for moreinformation on calculating the checksum.

4.9 Exiting Enhanced ICSP ModeExiting Program/Verify mode is done by removing VIHfrom MCLR, as illustrated in Figure 4-7. The onlyrequirement for exit is that an interval P16 shouldelapse between the last clock and program signals onPGECx and PGEDx before removing VIH.

FIGURE 4-7: EXITING ENHANCED ICSP™ MODE

Send PROGWCommand

IsPROGW response

PASS?

No

Yes

No

FailureReport Error

Start

End

Yes

LastConfiguration

Byte?

ConfigAddress =ConfigAddress + 2

MCLR

P16

PGEDx

PGEDx = Input

PGECx

VDD

VIH

VIH

P17



5.0 PROGRAMMING THE PROGRAMMING EXECUTIVETO MEMORY

5.1 OverviewIf it is determined that the programming executive is notpresent in executive memory (as described inSection 4.2 “Confirming the Presence of theProgramming Executive”), the programmingexecutive must be programmed to executive memory.

Figure 5-1 shows the high level process ofprogramming the programming executive intoexecutive memory. First, ICSP mode must be enteredand executive memory is erased, then theprogramming executive is programmed and verified.Lastly ICSP mode is exited.

FIGURE 5-1: HIGH-LEVEL PROGRAMMING EXECUTIVE PROGRAMMING FLOW

5.2 Erasing Executive MemoryThe procedure for erasing executive memory is similarto that of erasing program memory and is shown inFigure 5-2. It consists of setting NVMCON to 0x404F,initializing the TBLPAG register to the beginning ofexecutive memory; 0x80, and then executing theprogramming cycle.

Table 5-1 illustrates the ICSP programming process forErasing executive memory.

FIGURE 5-2: ERASE FLOW

Note: The Programming Executive (PE) can belocated within the following folder withinyour installation of MPLAB® IDE:...\Microchip\MPLAB IDE\REAL ICE,and then selecting the Hex PE file,RIPE_01d_xxxxxx.hex.

Start

End

Read/Verify the

Program the

Enter ICSP mode

Erase Executive



Memory

Exit ICSP mode

Note: The programming executive mustalways be erased before it isprogrammed, as described in Figure 5-1.

Start

End

Set the WR bit to Initiate Erase

Write 0x404F to NVMCON SFR

Delay P11 + P10 Time

Initialize the TBLPAG register to 0x80



TABLE 5-1: SERIAL INSTRUCTION EXECUTION FOR ERASING EXECUTIVE MEMORY4-bit Control



040200040200000000


Step 2: Set the NVMCON to erase all executive memory.00000000

2404FA883B0A

MOV #0x404F, W10MOV W10, NVMCON

Step 3: Initiate the TBLPAG register for executive memory.00000000

200800880191

MOV #0x80, W1MOV W1, TBLPAG

Step 4: Initiate the erase cycle.00000000000000000000

A8E761000000000000000000000000

BSET NVMCON, #WR NOPNOPNOPNOP

Step 5: Wait for Bulk Erase operation to complete and make sure the WR bit is clear.— — Externally time ‘P11’ ms (see Section 9.0 “AC/DC Characteristics and Timing

Requirements”) to allow sufficient time for the Bulk Erase operation to complete.



5.3 Program the Programming Executive

Storing the programming executive to executivememory is similar to normal programming of codememory. Namely, the executive memory must first beerased, and then the programming executive must beprogrammed one word at a time. This control flow issummarized in Figure 5-3.

Table 5-2 illustrates the ICSP programming process forprogramming executive memory.

FIGURE 5-3: PROGRAM CODE MEMORY FLOW

Start Write Sequence

Alllocations

done?

No

End

Start

Yes

and Poll for WR bitto be cleared

ConfigureDevice for

Writes

Load Lower Word and Upper Byte of instruction

to Write Latch and increment the Write Pointer

TABLE 5-2: PROGRAMMING THE PROGRAMMING EXECUTIVE4-bit Control


Step 1: Exit the Reset vector.

000000000000

040200040200000000


Step 2: Set the NVMCON register to program one executive memory word.

000000000000

240030000000883B00

MOV #0x4003, W0NOPMOV W0, NVMCON

Step 3: Initialize the TBLPAG register to the first page of executive memory.

000000000000

200801000000880191

MOV #0x80, W1NOPMOV W1, TBLPAG

Step 4: Initialize the write pointer (W2) for the TBLWT instruction.

0000 2xxxx2 MOV #<DestinationAddress15:0>, W2



Step 5: Load the lower instruction word to the W5 register and the upper instruction byte to the W6 register.

00000000

2xxxx5200xx6

MOV #<LOW_WORD>, W5MOV #<HIGH_BYTE>, W6

Step 6: Write the program memory low word and the executive memory upper byte into the write latch and incrementthe write pointer.

00000000000000000000000000000000

000000BB0905000000000000BBD906000000000000000000

NOPTBLWTL.W W5, [W2]NOPNOPTBLWTH.B W6, [W2++]NOPNOPNOP

Step 7: Initiate the write cycle.

00000000000000000000

A8E761000000000000000000000000


Step 8: Wait for the word write operation to complete and make sure the WR bit is clear.

—

0000000000000001

00000000

—

—

803B00883C20000000<VISI>

040200000000

—



GOTO 0x200NOP

Repeat until the WR bit is clear.

Step 9: Repeat steps 5-8 to write the remaining executive memory words.

TABLE 5-2: PROGRAMMING THE PROGRAMMING EXECUTIVE (CONTINUED)4-bit Control




5.4 Reading Executive MemoryReading from executive memory is performed by exe-cuting a series of TBLRD instructions and clocking outthe data using the REGOUT command.

Table 5-3 shows the ICSP programming details forreading executive memory.

To minimize programming time, the same packed dataformat that the programming executive uses is utilized.See Section 6.2 “Programming ExecutiveCommands” for more details on the packed dataformat.

TABLE 5-3: SERIAL INSTRUCTION EXECUTION FOR READING EXECUTIVE MEMORY

4-bit Control Code



040200040200000000



2008008801902xxxx6

MOV #0x80, W0MOV W0, TBLPAGMOV #<SourceAddress15:0>, W6

Step 3: Initialize the write pointer (W7) and store the next four locations of executive memory to W0:W5.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000

EB0380BA1B96000000000000BADBB6000000000000BADBD6000000000000BA1BB6000000000000BA1B96000000000000BADBB6000000000000BADBD6000000000000BA1BB6000000000000

CLR W7TBLRDL [W6], [W7++] NOPNOPTBLRDH.B [W6++], [W7++] NOPNOPTBLRDH.B [++W6], [W7++] NOPNOPTBLRDL [W6++], [W7++] NOPNOPTBLRDL [W6], [W7++] NOPNOPTBLRDH.B [W6++], [W7++] NOPNOPTBLRDH.B [++W6], [W7++] NOPNOPTBLRDL [W6++], [W7++] NOPNOP



Step 4: Output W0:W5 using the VISI register and REGOUT command.000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000

883C20000000<VISI>000000883C21000000<VISI>000000883C22000000<VISI>000000883C23000000<VISI>000000883C24000000<VISI>000000883C25000000<VISI>000000

MOV W0, VISI NOPClock out contents of VISI register.NOPMOV W1, VISI NOPClock out contents of VISI register.NOPMOV W2, VISI NOPClock out contents of VISI register.NOPMOV W3, VISI NOPClock out contents of VISI register.NOPMOV W4, VISI NOPClock out contents of VISI register.NOPMOV W5, VISI NOPClock out contents of VISI register.NOP


040200000000

GOTO 0x200 NOP

Step 6: Repeat step 3-5 until all desired executive memory is read.

TABLE 5-3: SERIAL INSTRUCTION EXECUTION FOR READING EXECUTIVE MEMORY (CONTINUED)

4-bit Control Code




5.5 Verify Programming ExecutiveThe verify step involves reading back the executivememory space and comparing it against the copy heldin the programmer’s buffer.

The verify process is illustrated in Figure 5-4. The lowerword of the instruction is read, and then the lower byteof the upper word is read and compared against theinstruction stored in the programmer's buffer. Refer toSection 5.4 “Reading Executive Memory” forimplementation details of reading executive memory.

FIGURE 5-4: VERIFY EXECUTIVE MEMORY FLOW

Read Low Word

Read High Byte

Does

= ExpectedData?

Allexecutive memory

verified?

No

Yes

No

Set TBLPTR = 0

Start

Yes

End

with Post-Increment

with Post-Increment

FailureReport Error

Instruction Word



6.0 THE PROGRAMMING EXECUTIVE

6.1 Programming Executive Communication

The programmer and programming executive have amaster-slave relationship, where the programmer isthe master programming device and the programmingexecutive is the slave.

All communication is initiated by the programmer in theform of a command. Only one command at a time canbe sent to the programming executive. In turn, theprogramming executive only sends one response tothe programmer after receiving and processing acommand. The programming executive command setis described in Section 6.2 “Programming ExecutiveCommands”. The response set is described inSection 6.3 “Programming Executive Responses”.

6.1.1 COMMUNICATION INTERFACE AND PROTOCOL

The Enhanced ICSP interface is a 2-wire SPI imple-mented using the PGECx and PGEDx pins. The PGECxpin is used as a clock input pin and the clock sourcemust be provided by the programmer. The PGEDx pin isused for sending command data to and receivingresponse data from the programming executive.

FIGURE 6-1: PROGRAMMING EXECUTIVE SERIAL TIMING

Since a 2-wire SPI is used, and data transmissions arebidirectional, a simple protocol is used to control thedirection of PGEDx. When the programmer completesa command transmission, it releases the PGEDx lineand allows the programming executive to drive this linehigh. The programming executive keeps the PGEDxline high to indicate that it is processing the command.

After the programming executive has processed thecommand, it brings PGEDx low (P9b) to indicate to theprogrammer that the response is available to beclocked out. The programmer can begin to clock outthe response after maximum wait (P9b) and it mustprovide the necessary amount of clock pulses toreceive the entire response from the programmingexecutive.

After the entire response is clocked out, theprogrammer should terminate the clock on PGECx untilit is time to send another command to the programmingexecutive. This protocol is illustrated in Figure 6-2.

6.1.2 SPI RATEIn Enhanced ICSP mode, the dsPIC33F family devicesoperate from the Fast Internal RC oscillator, which hasa nominal frequency of 7.3728 MHz. This oscillatorfrequency yields an effective system clock frequency of1.8432 MHz. To ensure that the programmer does notclock too fast, it is recommended that a 1.85 MHz clockbe provided by the programmer.

FIGURE 6-2: PROGRAMMING EXECUTIVE – PROGRAMMER COMMUNICATION PROTOCOL

Note: For Enhanced ICSP, all serial data istransmitted on the falling edge of PGECxand latched on the rising edge of PGECx.All data transmissions are sent to the MostSignificant bit first using 16-bit mode (seeFigure 6-1).

PGECx

PGEDx

1 2 3 11 13 15 161412

LSb14 13 12 11

4 5 6

MSb 123... 45

P2

P3

P1

P1BP1A

1 2 15 16 1 2 15 16

PGECx

PGEDx

PGECx = Input PGECx = Input (Idle)

Host TransmitsLast Command Word

PGEDx = Input PGEDx = Output

P8

1 2 15 16

MSB X X X LSB MSB X X X LSB MSB X X X LSB1 0

P9b

PGECx = InputPGEDx = Output

P9a

Programming ExecutiveProcesses Command Host Clocks Out Response

Note 1: A delay of 25 ms is required between commands.



6.1.3 TIME OUTSThe programming executive uses no Watchdog or timeout for transmitting responses to the programmer. If theprogrammer does not follow the flow controlmechanism using PGECx as described inSection 6.1.1 “Communication Interface and Proto-col”, it is possible that the programming executive willbehave unexpectedly while trying to send a responseto the programmer. Since the programming executivehas no time out, it is imperative that the programmercorrectly follow the described communication protocol.

As a safety measure, the programmer should use thecommand time outs identified in Table 6-1. If thecommand time out expires, the programmer shouldreset the programming executive and startprogramming the device again.

TABLE 6-1: PROGRAMMING EXECUTIVE COMMAND SET

Opcode Mnemonic Length(16-bit words) Time Out Description

0x0 SCHECK 1 1 ms Sanity check.

0x1 READC 3 1 ms Read an 8-bit word from the specified Device ID register.

0x2 READP 4 1 ms/word Read ‘N’ 24-bit instruction words of code memory starting from the specified address.

0x3 Reserved N/A N/A This command is reserved. It will return a NACK.


0x5 PROGP 99 5 ms Program 64 instruction words of program memory at the specified starting address and verify.




0x9 ERASEP 3 20 ms Command to erase a page.

0xA Reserved N/A N/A This command is reserved. It will return a NACK.

0xB QVER 1 1 ms Query the programming executive software version.

0xC CRCP 5 1s Performs a CRC-16 on the specified range of program memory.

0xD PROGW 4 5 ms Program one instruction word of code memory at the specified address, and then verify.

0xE QBLANK 5 700 ms Query to check whether the code memory is blank.



6.2 Programming Executive Commands

The programming executive command set is shown inTable 6-1. This table contains the opcode, mnemonic,length, time out and description for each command.Functional details on each command are provided inthe command descriptions (Section 6.2.4 “CommandDescriptions”).

6.2.1 COMMAND FORMATAll programming executive commands have a generalformat consisting of a 16-bit header and any requireddata for the command (see Figure 6-3). The 16-bitheader consists of a 4-bit opcode field, which is used toidentify the command, followed by a 12-bit commandlength field.

FIGURE 6-3: COMMAND FORMAT

The command opcode must match one of those in thecommand set. Any command that is received whichdoes not match the list in Table 6-1 will return a “NACK”response (see Section 6.3.1.1 “Opcode Field”).

The command length is represented in 16-bit wordssince the SPI operates in 16-bit mode. Theprogramming executive uses the command length fieldto determine the number of words to read from the SPIport. If the value of this field is incorrect, the commandwill not be properly received by the programmingexecutive.

6.2.2 PACKED DATA FORMATWhen 24-bit instruction words are transferred acrossthe 16-bit SPI interface, they are packed to conservespace using the format illustrated in Figure 6-4. Thisformat minimizes traffic over the SPI and provides theprogramming executive with data that is properlyaligned for performing table write operations.

FIGURE 6-4: PACKED INSTRUCTION WORD FORMAT

6.2.3 PROGRAMMING EXECUTIVE ERROR HANDLING

The programming executive will “NACK” allunsupported commands. Additionally, due to thememory constraints of the programming executive, nochecking is performed on the data contained in theprogrammer command. It is the responsibility of theprogrammer to command the programming executivewith valid command arguments or the programmingoperation may fail. Additional information on errorhandling is provided in Section 6.3.1.3 “QE_CodeField”.

15 12 11 0

Opcode Length

Command Data First Word (if required)

•

•

Command Data Last Word (if required)

Note: When the number of instruction wordstransferred is odd, MSB2 is zero andLSW2 cannot be transmitted.

15 8 7 0

LSW1

MSB2 MSB1

LSW2

LSWx: Least Significant 16 bits of instruction wordMSBx: Most Significant Byte of instruction word



6.2.4 COMMAND DESCRIPTIONSAll commands supported by the programming executiveare described in Section 6.2.4.1 “SCHECK Command”through Section 6.2.4.6 “QVER Command”.

6.2.4.1 SCHECK Command

The SCHECK command instructs the programmingexecutive to do nothing but generate a response. Thiscommand is used as a “Sanity Check” to verify that theprogramming executive is operational.

Expected Response (2 words):0x10000x0002

6.2.4.2 READC Command

The READC command instructs the programmingexecutive to read N Device ID registers, starting fromthe 24-bit address specified by Addr_MSB andAddr_LS. This command can only be used to read 8-bitor 16-bit data.

When this command is used to read Device IDregisters, the upper byte in every data word returned bythe programming executive is 0x00 and the lower bytecontains the Device ID register value.

Expected Response (4 + 3 * (N – 1)/2 words for N odd):0x11002 + NDevice ID Register 1... Device ID Register N

15 12 11 0Opcode Length

Field Description

Opcode 0x0Length 0x1

Note: This instruction is not required forprogramming, but is provided fordevelopment purposes only.

15 12 11 8 7 0Opcode Length

N Addr_MSBAddr_LS

Field Description

Opcode 0x1Length 0x3N Number of 16-bit Device ID registers to

read (maximum of 256).Addr_MSB MSB of 24-bit source address.Addr_LS Least Significant 16 bits of 24-bit

source address.

Note: Reading unimplemented memory willcause the programming executive toreset. Please ensure that only memorylocations present on a particular deviceare accessed.



6.2.4.3 READP Command

The READP command instructs the programmingexecutive to read N 24-bit words of code memory,starting from the 24-bit address specified by Addr_MSBand Addr_LS. This command can only be used to read24-bit data. All data returned in the response to thiscommand uses the packed data format described inSection 6.2.2 “Packed Data Format”.

Expected Response (2 + 3 * N/2 words for N even):0x12002 + 3 * N/2Least significant program memory word 1... Least significant data word N

Expected Response (4 + 3 * (N – 1)/2 words for N odd):0x12004 + 3 * (N – 1)/2Least significant program memory word 1... MSB of program memory word N (zero padded)

6.2.4.4 PROGP Command

The PROGP command instructs the programmingexecutive to program 64 instruction words starting atthe specified memory address.

The data to program the memory, located in commandwords D_1 through D_96, must be arranged using thepacked instruction word format illustrated in Figure 6-4.

After all data has been programmed to code memory,the programming executive verifies the programmeddata against the data in the command.



NReserved Addr_MSB

Addr_LS

Field Description

Opcode 0x2Length 0x4N Number of 24-bit instructions to read

(maximum of 32768).Reserved 0x0Addr_MSB MSB of 24-bit source address.Addr_LS Least Significant 16 bits of 24-bit

source address.

Note: Reading unimplemented memory willcause the programming executive toreset. Please ensure that only memorylocations present on a particular deviceare accessed.


Reserved Addr_MSBAddr_LS

D_1D_2...

D_N

Field Description

Opcode 0x5Length 0x63Reserved 0x0Addr_MSB MSB of 24-bit destination address.Addr_LS Least Significant 16 bits of 24-bit

destination address.D_1 16-bit data word 1.D_2 16-bit data word 2.... 16-bit data word 3 through 95.D_96 16-bit data word 96.

Note: Refer to Table 2-2 for code memory sizeinformation.



6.2.4.5 ERASEP Command

The ERASEP command instructs the programmingexecutive to page erase [NUM_PAGES] of code mem-ory. The code memory must be erased at an “even” 512instruction word address boundary


6.2.4.6 QVER Command

The QVER command queries the version of theprogramming executive software stored in testmemory. The “version.revision” information is returnedin the response’s QE_Code using a single byte with thefollowing format: main version in upper nibble andrevision in the lower nibble (i.e., 0x23 meansversion 2.3 of programming executive software).

Expected Response (2 words):0x1BMN (where “MN” stands for version M.N)0x0002

15 12 11 8 7 0

Opcode Length

NUM_PAGES Addr_MSB

Addr_LS

Field Description

Opcode 0x9Length 0x3NUM_PAGES Up to 255Addr_MSB Most Significant Byte of the 24-bit

addressAddr_LS Least Significant 16 bits of the 24-bit

address


Field Description

Opcode 0xBLength 0x1



6.2.4.7 CRCP Command

The CRCP command performs a CRC-16 on the rangeof memory specified. This command can substitute fora full chip verify. Data is shifted in a packed method asdemonstrated in Figure 6-4, byte-wise LeastSignificant Byte first.

Example:CRC-CCITT-16 with test data of “123456789” becomes0x29B1

Expected Response (3 words):QE_Code: 0x1C00

Length: 0x0003

CRC Value: 0xXXXX

6.2.4.8 PROGW Command

The PROGW command instructs the programmingexecutive to program one instruction word of codememory (3 bytes) to the specified memory address.

After the word has been programmed to code memory,the programming executive verifies the programmeddata against the data in the command.

Expected Response (2 words):0x1D000x0002

15 12 11 8 7 0

Opcode Length

Reserved Addr_MSB

Addr_LSW

Reserved Size_MSB

Size_LSW

Field Description

Opcode 0xCLength 0x5Reserved 0x0Addr_MSB Most Significant Byte of 24-bit

addressAddr_LSW Least Significant 16 bits of 24-bit

addressSize Number of 24-bit locations (address

range divided by 2)


Data_MSB Addr_MSBAddr_LSData_LS

Field Description

Opcode 0xDLength 0x4Data_MSB MSB of 24-bit data.Addr_MSB MSB of 24-bit destination address.Addr_LS Least Significant 16 bits of 24-bit

destination address.Data_LS Least Significant 16 bits of 24-bit data



6.2.4.9 QBLANK Command

The QBLANK command queries the programmingexecutive to determine if the contents of code memoryare blank (contains all ‘1’s). The size of code memoryto check must be specified in the command.

The Blank Check for code memory begins at [Addr] andadvances toward larger addresses for the specifiednumber of instruction words.

QBLANK returns a QE_Code of 0xF0 if the specifiedcode memory is blank; otherwise, QBLANK returns aQE_Code of 0x0F.

Expected Response (2 words for blank device):0x1EF00x0002

Expected Response (2 words for non-blank device):0x1E0F0x0002


Reserved Size_MSBSize_LSW

Reserved Addr_MSBAddr_LSW

Field Description

Opcode 0xELength 0x5Size Length of program memory to check

(in 24-bit words) + Addr_MSAddr_MSB Most Significant Byte of the 24-bit

addressAddr_LSW Least Significant 16 bits of the 24-bit

address

Note: Ensure that the address range selectedexcludes the configuration bytes at the topof memory when using the QBLANK com-mand; otherwise, a non-blank responsewill be generated.



6.3 Programming Executive Responses

The programming executive sends a response to theprogrammer for each command that it receives. Theresponse indicates if the command was processedcorrectly. It includes any required response data orerror data.

The programming executive response set is shown inTable 6-2. This table contains the opcode, mnemonicand description for each response. The response formatis described in Section 6.3.1 “Response Format”.

TABLE 6-2: PROGRAMMING EXECUTIVE RESPONSE OPCODES

6.3.1 RESPONSE FORMATAll programming executive responses have a generalformat consisting of a two-word header and anyrequired data for the command.

6.3.1.1 Opcode FieldThe opcode is a 4-bit field in the first word of theresponse. The opcode indicates how the commandwas processed (see Table 6-2). If the command wasprocessed successfully, the response opcode is PASS.If there was an error in processing the command, theresponse opcode is FAIL and the QE_Code indicatesthe reason for the failure. If the command sent tothe programming executive is not identified, theprogramming executive returns a NACK response.

Opcode Mnemonic Description

0x1 PASS Command successfully processed.

0x2 FAIL Command unsuccessfully processed.

0x3 NACK Command not known.

Field Description

Opcode Response opcode.Last_Cmd Programmer command that

generated the response.QE_Code Query code or error code.Length Response length in 16-bit words

(includes 2 header words).D_1 First 16-bit data word (if applicable).D_N Last 16-bit data word (if applicable).

15 12 11 8 7 0

Opcode Last_Cmd QE_Code

Length

D_1 (if applicable)

...

D_N (if applicable)



6.3.1.2 Last_Cmd FieldThe Last_Cmd is a 4-bit field in the first word ofthe response and indicates the command that theprogramming executive processed. Since theprogramming executive can only process onecommand at a time, this field is technically not required.However, it can be used to verify that the programmingexecutive correctly received the command that theprogrammer transmitted.

6.3.1.3 QE_Code FieldThe QE_Code is a byte in the first word of theresponse. This byte is used to return data for querycommands and error codes for all other commands.

When the programming executive processes one of thetwo query commands (QBLANK or QVER), the returnedopcode is always PASS and the QE_Code holds thequery response data. The format of the QE_Code forboth queries is shown in Table 6-3.

TABLE 6-3: QE_Code FOR QUERIES

When the programming executive processes anycommand other than a Query, the QE_Coderepresents an error code. Supported error codes areshown in Table 6-4. If a command is successfullyprocessed, the returned QE_Code is set to 0x0, whichindicates that there is no error in the commandprocessing. If the verify of the programming for thePROGW command fails, the QE_Code is set to 0x1. Forall other programming executive errors, the QE_Codeis 0x2.

TABLE 6-4: QE_Code FOR NON-QUERY COMMANDS

6.3.1.4 Response LengthThe response length indicates the length of theprogramming executive’s response in 16-bit words.This field includes the 2 words of the response header.

With the exception of the response for the readcommands, the length of each response is only 2words.

The response to the read commands uses the packedinstruction word format described in Section 6.2.2“Packed Data Format”. When reading an odd num-ber of program memory words (N odd), the responseto the READP command is (3 * (N + 1)/2 + 2) words.When reading an even number of program memorywords (N even), the response to the READP commandis (3 * N/2 + 2) words.

Query QE_Code

QBLANK 0x0F = Code memory is NOT blank0xF0 = Code memory is blank

QVER 0xMN, where programming executive software version = M.N(i.e., 0x32 means software version 3.2)

QE_Code Description

0x0 No error. 0x1 Verify failed.0x2 Other error.



7.0 DEVICE IDThe device ID region of memory can be used todetermine variant and manufacturing information aboutthe chip. This region of memory is read-only and can beread when code protection is enabled.

Table 7-1 lists the identification information for eachdevice. Table 7-2 shows the Device ID registers.

TABLE 7-2: DEVICE ID REGISTERS

TABLE 7-1: DEVICE IDs AND REVISION

Device DEVID Register Value Application ID DEVREV Register Value and Silicon Revision

dsPIC33FJ16GP101 0x0200 0xCD

0x3001 – A1 RevisiondsPIC33FJ16GP102 0x0201 0xCDdsPIC33FJ16MC101 0x0202 0xCDdsPIC33FJ16MC102 0x0203 0xCDdsPIC33FJ06GS001 0x4900 0xCD

0x3000 – A0 RevisiondsPIC33FJ06GS101A 0x4901 0xCDdsPIC33FJ06GS102A 0x4904 0xCDdsPIC33FJ06GS202A 0x4905 0xCDdsPIC33FJ09GS302 0x4906 0xCD

Address NameBit

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0xFF0000 DEVID DEVID Value

0xFF0002 DEVREV DEVREV Value



8.0 CHECKSUM COMPUTATIONChecksums for the devices listed below are 16 bits insize. The checksum is calculated by summing thefollowing:

• Contents of code memory locations• Contents of Configuration words

All memory locations are summed one byte at a timeusing only their native data size. Configuration bytesare summed by adding the lower two bytes of theselocations (the upper byte is ignored), while codememory is summed by adding all three bytes of codememory.

Table 8-1 is an example of the checksum calculation forthe dsPIC33FJ16MC102 device.

Table 8-2 describes the Configuration bit masks for thedsPIC33FJ16GP/MC10X devices.

TABLE 8-2: dsPIC33FJ16GP/MC10X CONFIGURATION BIT MASKS

Table 8-3 describes the configuration bit masks for thedsPIC33FJ06GS001, dsPIC33FJ06GSX0XA, anddsPIC33FJ09GS302 devices.

TABLE 8-1: CHECKSUM COMPUTATION EXAMPLE

Device Read CodeProtection Checksum Computation Erased

Value

Value with0xAAAAAA at 0x0

and LastCode Address

dsPIC33FJ16MC102 Disabled CFGB + SUM(0:0x002BFA) 0xF804 0xF606

Enabled Reads of PM return 0x00 0x0000 0x0000

Item Description:SUM(a:b) = Byte sum of locations a to b inclusive (all 3 bytes of code memory)CFGB = Configuration block (masked) = Byte sum of (CONFIG1 & 0x3FFF + CONFIG2 & 0xFFFF)CFGB = Configuration block (masked) = Byte sum of ((0x7FFF & 0x3FFF) + (0xFFFF & 0xFFFF))

Device: CONFIG2 CONFIG1

dsPIC33FJ16GP101 0xFFFF 0x3FFFdsPIC33FJ16GP102 0xFFFF 0x3FFFdsPIC33FJ16MC101 0xFFFF 0x3FFFdsPIC33FJ16MC102 0xFFFF 0x3FFF

TABLE 8-3: dsPIC33FJ06GS001, dsPIC33FJ06GSX0XA, AND dsPIC33FJ09GS302 CONFIGURATION BIT MASKS

Device FICD FWDT FOSC FOSCSEL FGSdsPIC33FJ06GS001 0xA3 0xBF 0xE7 0x87 0x03dsPIC33FJ06GS101A 0xA3 0xBF 0xE7 0x87 0x03dsPIC33FJ06GS102A 0xA3 0xBF 0xE7 0x87 0x03dsPIC33FJ06GS202A 0xA3 0xBF 0xE7 0x87 0x03dsPIC33FJ09GS302 0xA3 0xBF 0xE7 0x87 0x03



9.0 AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS

Table 9-1 lists the AC/DC characteristics and timingrequirements.

TABLE 9-1: AC/DC CHARACTERISTICS AND TIMING REQUIREMENTSStandard Operating ConditionsOperating Temperature: -40ºC to +85ºC. Programming at +25ºC is recommended.

Param. No. Symbol Characteristic Min. Max. Units Conditions

D111 VDD Supply Voltage During Programming 3.0 3.60 V Normal programming(1)

D112 IPP Programming Current on MCLR — 5 μA —

D113 IDDP Supply Current During Programming — 10 mA —

D114 IPEAK Instantaneous Peak Current During Start-up — 45 mA —

D031 VIL Input Low Voltage VSS 0.2 VDD V —

D041 VIH Input High Voltage 0.8 VDD VDD V —

D080 VOL Output Low Voltage — 0.4 V IOL = 8 mA @ 3.3V

D090 VOH Output High Voltage 2.4 — V IOH = -8 mA @ 3.3V

D012 CIO Capacitive Loading on I/O pin (PGEDx) — 50 pF To meet AC specifications

P1 TPGC Serial Clock (PGECx) Period (ICSP™) 200 — ns —

P1 TPGC Serial Clock (PGECx) Period (Enhanced ICSP) 500 — ns —

P1A TPGCL Serial Clock (PGECx) Low Time (ICSP) 80 — ns —

P1A TPGCL Serial Clock (PGECx) Low Time (Enhanced ICSP)

200 — ns —

P1B TPGCH Serial Clock (PGECx) High Time (ICSP) 80 — ns —

P1B TPGCH Serial Clock (PGECx) High Time (Enhanced ICSP)

200 — ns —

P2 TSET1 Input Data Setup Time to Serial Clock ↓ 15 — ns —

P3 THLD1 Input Data Hold Time from PGECx ↓ 15 — ns —

P4 TDLY1 Delay between 4-bit Command and Command Operand

40 — ns —

P4A TDLY1A Delay between Command Operand and Next 4-bit Command

40 — ns —

P5 TDLY2 Delay between Last PGECx ↓ of Command to First PGECx ↑ of Read of Data Word

20 — ns —

P6 TSET2 VDD ↑ Setup Time to MCLR ↑ 100 — ns —

P7 THLD2 Input Data Hold Time from MCLR ↑ 25 — ms —

P8 TDLY3 Delay between Last PGECx ↓ of Command Byte to PGEDx ↑ by Programming Executive

12 — μs —

P9a TDLY4 Programming Executive Command Processing Time

10 — μs —

Note 1: VDD must also be supplied to the AVDD pins during programming. AVDD and AVSS should always be within±0.3V of VDD and VSS, respectively.

2: Time depends on the FRC accuracy and the value of the FRC Oscillator tuning register. Refer to the“Electrical Characteristics” section in the specific device data sheet.

3: This time applies to both Program Memory words and Configuration words.



P9b TDLY5 Delay between PGEDx ↓ by Programming Executive to PGEDx Released by Programming Executive

15 23 μs —

P10 TDLY6 PGECx Low Time After Programming 400 — ns —

P11 TDLY7 Bulk Erase Time 200 240 ms See Note 2P12 TDLY8 Page Erase Time 20.1 26.5 ms See Note 2P13 TDLY9 Word Programming Time 47.9 — μs See Note 2 and Note 3

P14 TR MCLR Rise Time to Enter ICSP mode — 1.0 μs —

P15 TVALID Data Out Valid from PGECx ↑ 10 — ns —

P16 TDLY10 Delay between Last PGECx ↓ and MCLR ↓ 0 — s —

P17 THLD3 MCLR ↓ to VDD ↓ 100 — ns —

P18 TKEY1 Delay from First MCLR ↓ to First PGECx ↑ for Key Sequence on PGEDx

1 — ms —

P19 TKEY2 Delay from Last PGECx ↓ for Key Sequence on PGEDx to Second MCLR ↑

25 — ns —

P21 TMCLRH MCLR High Time — 500 μs —

TABLE 9-1: AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS (CONTINUED)Standard Operating ConditionsOperating Temperature: -40ºC to +85ºC. Programming at +25ºC is recommended.

Param. No. Symbol Characteristic Min. Max. Units Conditions

Note 1: VDD must also be supplied to the AVDD pins during programming. AVDD and AVSS should always be within±0.3V of VDD and VSS, respectively.

2: Time depends on the FRC accuracy and the value of the FRC Oscillator tuning register. Refer to the“Electrical Characteristics” section in the specific device data sheet.

3: This time applies to both Program Memory words and Configuration words.



NOTES:



APPENDIX A: HEX FILE FORMATFlash programmers process the standard HEX formatused by the Microchip development tools. The formatsupported is the Intel® HEX32 Format (INHX32).Please refer to Appendix A in the “MPASM™ User’sGuide” (DS33014) for more information about hex fileformats.

The basic format of the hex file is:

:BBAAAATTHHHH...HHHHCC

Each data record begins with a 9-character prefix andalways ends with a 2-character checksum. All recordsbegin with ‘:’ regardless of the format. The individualelements are described below.

• BB – is a two-digit hexadecimal byte count representing the number of data bytes that appear on the line. Divide this number by two to get the number of words per line.

• AAAA – is a four-digit hexadecimal address representing the starting address of the data record. Format is high byte first followed by low byte. The address is doubled because this format only supports 8 bits. Divide the value by two to find the real device address.

• TT – is a two-digit record type that will be ‘00’ for data records, ‘01’ for end-of-file records and ‘04’ for extended-address record.

• HHHH – is a four-digit hexadecimal data word. Format is low byte followed by high byte. There will be BB/2 data words following TT.

• CC – is a two-digit hexadecimal checksum that is the two’s complement of the sum of all the preceding bytes in the line record.

Because the Intel hex file format is byte-oriented, andthe 16-bit program counter is not, program memorysections require special treatment. Each 24-bit pro-gram word is extended to 32 bits by inserting aso-called “phantom byte”. Each program memoryaddress is multiplied by 2 to yield a byte address.

As an example, a section that is located at 0x100 inprogram memory will be represented in the hex file as0x200.

The hex file will be produced with the followingcontents:

:020000040000fa

:040200003322110096

:00000001FF

Notice that the data record (line 2) has a load addressof 0200, while the source code specified address0x100. Note also that the data is represented in“little-endian” format, meaning the Least SignificantByte (LSB) appears first. The phantom byte appearslast, just before the checksum.



APPENDIX B: REVISION HISTORY

Revision A (April 2011)This is the initial released version of this document.

Revision B (July 2011)This revision includes the following updates:

• Changed to document title to: dsPIC33F Flash Programming Specification for Devices with Volatile Configuration Bits

• Bit 14 of CONFIG1 was changed to Reserved and Note 5 was removed in dsPIC33FJ16GP/MC10X Configuration Bits (see Table 2-3)

• Removed the JTAG ID column from Device IDs and Revision (see Table 7-1)

• Removed the JTAG ID Register (Table 7-2)• Updated the values for Read Code Protection

when Disabled, and updated both CFGB byte sum values from 0x7FFF to 0x3FFF in the Checksum Computation Example (see Table 8-1)

• Updated the CONFIG1 dsPIC33FJ16GP/MC10X Configuration Bit Masks values from 0x7FFF to 0x3FFF (see Table 8-1)

• Updated the the following AD/DC Characteristics and Timing Requirements (see Table 9-1)- Maximum value for parameter D113 was

changed- Added parameter D114- Maximum value and conditions for parameter

D80 were changed- Minimum value and conditions for parameter

D90 were changed


Note the following details of the code protection feature on Microchip devices:• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyer’s risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights.

© 2011 Microchip Technology Inc.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

© 2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.

Printed on recycled paper.

ISBN: 978-1-61341-387-6

DS70659B-page 51

Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.


AMERICASCorporate Office2355 West Chandler Blvd.Chandler, AZ 85224-6199Tel: 480-792-7200 Fax: 480-792-7277Technical Support: http://www.microchip.com/supportWeb Address: www.microchip.comAtlantaDuluth, GA Tel: 678-957-9614 Fax: 678-957-1455BostonWestborough, MA Tel: 774-760-0087 Fax: 774-760-0088ChicagoItasca, IL Tel: 630-285-0071 Fax: 630-285-0075ClevelandIndependence, OH Tel: 216-447-0464 Fax: 216-447-0643DallasAddison, TX Tel: 972-818-7423 Fax: 972-818-2924DetroitFarmington Hills, MI Tel: 248-538-2250Fax: 248-538-2260IndianapolisNoblesville, IN Tel: 317-773-8323Fax: 317-773-5453Los AngelesMission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608Santa ClaraSanta Clara, CA Tel: 408-961-6444Fax: 408-961-6445TorontoMississauga, Ontario, CanadaTel: 905-673-0699 Fax: 905-673-6509

ASIA/PACIFICAsia Pacific OfficeSuites 3707-14, 37th FloorTower 6, The GatewayHarbour City, KowloonHong KongTel: 852-2401-1200Fax: 852-2401-3431Australia - SydneyTel: 61-2-9868-6733Fax: 61-2-9868-6755China - BeijingTel: 86-10-8569-7000 Fax: 86-10-8528-2104China - ChengduTel: 86-28-8665-5511Fax: 86-28-8665-7889China - ChongqingTel: 86-23-8980-9588Fax: 86-23-8980-9500China - HangzhouTel: 86-571-2819-3180 Fax: 86-571-2819-3189China - Hong Kong SARTel: 852-2401-1200 Fax: 852-2401-3431China - NanjingTel: 86-25-8473-2460Fax: 86-25-8473-2470China - QingdaoTel: 86-532-8502-7355Fax: 86-532-8502-7205China - ShanghaiTel: 86-21-5407-5533 Fax: 86-21-5407-5066China - ShenyangTel: 86-24-2334-2829Fax: 86-24-2334-2393China - ShenzhenTel: 86-755-8203-2660 Fax: 86-755-8203-1760China - WuhanTel: 86-27-5980-5300Fax: 86-27-5980-5118China - XianTel: 86-29-8833-7252Fax: 86-29-8833-7256China - XiamenTel: 86-592-2388138 Fax: 86-592-2388130China - ZhuhaiTel: 86-756-3210040 Fax: 86-756-3210049

ASIA/PACIFICIndia - BangaloreTel: 91-80-3090-4444 Fax: 91-80-3090-4123India - New DelhiTel: 91-11-4160-8631Fax: 91-11-4160-8632India - PuneTel: 91-20-2566-1512Fax: 91-20-2566-1513Japan - YokohamaTel: 81-45-471- 6166 Fax: 81-45-471-6122Korea - DaeguTel: 82-53-744-4301Fax: 82-53-744-4302Korea - SeoulTel: 82-2-554-7200Fax: 82-2-558-5932 or 82-2-558-5934Malaysia - Kuala LumpurTel: 60-3-6201-9857Fax: 60-3-6201-9859Malaysia - PenangTel: 60-4-227-8870Fax: 60-4-227-4068Philippines - ManilaTel: 63-2-634-9065Fax: 63-2-634-9069SingaporeTel: 65-6334-8870Fax: 65-6334-8850Taiwan - Hsin ChuTel: 886-3-6578-300Fax: 886-3-6578-370Taiwan - KaohsiungTel: 886-7-213-7830Fax: 886-7-330-9305Taiwan - TaipeiTel: 886-2-2500-6610 Fax: 886-2-2508-0102Thailand - BangkokTel: 66-2-694-1351Fax: 66-2-694-1350

EUROPEAustria - WelsTel: 43-7242-2244-39Fax: 43-7242-2244-393Denmark - CopenhagenTel: 45-4450-2828 Fax: 45-4485-2829France - ParisTel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79Germany - MunichTel: 49-89-627-144-0 Fax: 49-89-627-144-44Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781Netherlands - DrunenTel: 31-416-690399 Fax: 31-416-690340Spain - MadridTel: 34-91-708-08-90Fax: 34-91-708-08-91UK - WokinghamTel: 44-118-921-5869Fax: 44-118-921-5820

Worldwide Sales and Service

05/02/11

http://support.microchip.com

http://www.microchip.com

dspic33f flash programming ... -...

Documents