Department of Computer ScienceNational Tsing Hua University
Chih-Tsun Huang (黃稚存)http://nthucad.cs.nthu.edu.tw/~cthuang/
Chapter 6Registers and Counters
Outline
Registers Shift Registers
Counters Ripple Counters
Synchronous Counters
Other Counters
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Introduction
Registers A group of binary cells (FFs) suitable for holding
binary data information In addition to the FFs, a register may have
combinational gates to control when and how the new information is transferred into the register
Counters A register that goes through a predetermined
sequence of states upon the application of input pulses
The gates in a counter are connected in such a way as to produce a predefined sequence of binary states in the register
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Registers (1/2) A register can be viewed as a bitwise extension of a FF
The simplest of the storage components: n inputs, n outputs, and a clock signal
All the n FFs are driven by the common clock signal
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Registers (2/2) The register may be enhanced by asynchronous Preset
and Clear (Reset) signals, which are not controlled by the clock signal
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Registers with Parallel Load (1/2) 4-bit register
with parallel load
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Registers with Parallel Load (1/2) To control when the data will be entered into a
register, and for how long it will be stored before being sent to the output
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Shift Registers
A shift register can shift its stored data right and/or left.
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Serial Transfer Serial transfer vs. parallel transfer
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All bits at the same time
Serial Adder Using D Flip-Flops Initially, augend is in register
A and addend is in register B
Shift control enables the triggering of clock and 1-bit addition of two operands from LSB to MSB.
A new sum (S) bit is transferred to shift register A
A carry-out (C) of the FA is transferred to Q as the z input of the next addition
Finally, when the shift control is disabled, summation result is stored in shift register A.
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Universal Shift Register (1/3)
Shift register types Unidirectional shift register Shift in one direction
Bidirectional shift register Shift in both direction
Universal shift register Capable of both-direction shifting and parallel load/out
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Universal Shift Register (2/3)
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Universal Shift Register (3/3)
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Counters Counter is a special type of register that
counts upward, downward, or in any pre-specified sequence. Ripple counters (asynchronous counter) The output transition of flip-flop serves as a source for
triggering other flip-flops
Synchronous counters The clock inputs of all flip-flops receive a common
clock
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Binary Ripple Counter (1/4)
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With T flip-flops With D flip-flops
Binary Ripple Counter (2/4) With D FFs
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Binary Ripple Counter (3/4) With T FFs
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Binary Ripple Counter (4/4) Down counter with T FFs Replace active-low clock with active-high clock
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BCD Ripple Counter
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Three Decade BCD Counter When Q8 in one decade goes from 1 to 0, it
triggers the count for the next higher decade while it own decade goes from 9 to 0.
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4-bit Synchronous Binary Counter
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4-bit Up/Down Binary Counter
Up=1, Down=0
Up=0, Down=1
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4-bit Binary Counter with Parallel Load (1/2)
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4-bit Binary Counter with Parallel Load (2/2)
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BCD Counters (1/2)
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BCD Counters (2/2)
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Counters with Unused States (1/3)
n flops => 2n states Unused states States that are not used in specifying the FSM May be treated as don’t-care conditions or may be
assigned specific next states
Self-correcting counters Ensure that when a circuit enters one of its
unused states, it eventually goes into one of the valid states after one or more clock pulses so that it can resume normal operation Analyze the circuit to determine the next state from an
unused state after it is designed
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Counters with Unused States (2/3)
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Counters with Unused States (3/3)
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Ring Counter A circular shift register with only one flip-flop
being set at any particular time, all others are cleared. (initial value 1000...000)
The single bit is shifted from one flip-flop to the next to produce the sequence of timing signals
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A2 A2 A1 A0
1 0 0 0
0 1 0 0
0 0 1 0
0 0 0 1
1 0 0 0
Ring Counter Applications
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Johnson Counter Ring counter vs. Switch-tail ring counter Ring counter A k-bit ring counter circulates a single bit among the
flip-flops to provide k distinguishable states
Switch-tail ring counter A circular shift register with its complement output of
the last flip-flop connected to the input of the first flip-flop.
A k-bit switch-tail ring counter will go through a sequence of 2k distinguishable states (initial value 0 0 ... 0)
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