do an lap trinh c cho ho vi dieu khien 8051

8/2/2019 Do an Lap Trinh c Cho Ho Vi Dieu Khien 8051

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B CNG NGHIPTRNG I HC CNG NGHIP TP HCM

KHOA CNG NGHIN T

n Tt nghip

Ti:

LP TRNH C CHO H VI IU KHIN 8051


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SVTH:L Vn Long & ng c Trung CDDT6K Trang 2

PHN I

TNG QUAN v TI

I. T VN :Ngy nay, nhng ng dng ca Vi iu khin i su vo i sng sinh hot v

sn xut ca con ngi. Thc t hin nay l hu ht cc thit bin dn dng hin nayu c s gp mt ca Vi iu Khin v vi x l . ng dng vi iu khin trong thit kh thng lm gim chi ph thit k v h gi thnh sn phm ng thi nng cao tnh nnh ca thit b v h thng.Trn th trng c rt nhiu h vi iu khin: h 8051 caIntel, 68HC11 ca Motorola, Z80 ca hng Zilog, PIC ca hng Microchip, H8 caHitachi,vv

Vic pht trin ng dng cc h vi x l i hi nhng hiu bit c v phn cngcng nh phn mm, nhng cng chnh v vy m cc h vi x l c s dng giiquyt nhng bi ton rt khc nhau. Tnh a dng ca cc ng dng ph thuc vo vicla chn cc h vi x l c th cng nh vo k thut lp trnh.

Ngy nay cc b vi x l c mt trong rt nhiu thit bin t hin i: tua CD, my thu hnh, my ghi hnh, dn m thanh HiFi, biu khin l si cho ncc thit biu khin dng trong cng nghip. Lnh vc ng dng ca cc h vi x lcng rt rng ln: t nguyn cu khoa hc, truyn d liu, n cng nghip, nng lng,giao thng v y t

Ty theo kinh nghim v mc thng tho m chng ta c th s dng cc ngnng khc ngoi hp ng nh: C, C++, Visual basic c nhng chng trnh cht lngcao hn.

II. NI DUNG CA TI: Slc v vi iu khin AT89C51. Kho st vi iu khin AT89C2051 ca hng ATMEL.

Gm s chn linh kin. S khi ca AT89C2051. Cc ni dng ng dng ca AT89C2051.

Gii thiu phn mm Keil Software ViSion 2 ng dng ngn ng C v Assembly iu khin lp trnh led.

ng dng cho led n, led 7 on, led ma trn Kt lun v hng pht trin ca ti.


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PHN II

NI DUNG TICHNG 1:GII THIU B VI IU KHIN 89C2051 v 89C51

I.GII THIU B VI IU KHIN 89C2051

I.1 CC C IM Tng thch vi cc sn phm ca h MSC-51. 2K byte b nhFlash lp trnh c. Kh nng :1000 chu k ghi/xa. Tm in p hot ng t 2,7 V n 6V Tm tn s hot ng t 0 Hz n 21 MHz 2 mc kha b nhchng trnh (program memory). RAM bn trong (internal RAM) c dung lng 128 x 8 bit. 15 ng I/O lp trnh c.

2 bnh thi /m 16 bit. 6 ngun (nguyn nhn ) ngt. Knh ni tip UART lp trnh c. Cc ng ra kch LED trc tip. Mch so snh tng t trn chip (on-chip analog comparator). Cc ch ngh cng sut thp v ch gim cng sut.

I.2M TChip AT89C2051 l chip vi iu khin CMOS 8 bit in p thp, hiu sut cao c 2K

byte b nhFlash chc, xa c v lp trnh c PEROM (Flash programmable anderasable readonly memory). Linh kin ny c sn xut bng cch s dng cng ngh b nhkhng thay i mt cao ca Atmel v tng thch vi tp tp ca MCS-51 chun cng

nghip. Bng cch kt hp mt CPU 8-bit a nng v linh hot vi Flash trn chip n tinh th ,Atmel AT89C2051 l chip vi iu khin mnh cung cp gii php linh ng cao v mang lihiu qu v gi thnh cho nhiu ng dng iu khin nhng (embedded control application).

AT89C2051 cung cp cc c tnh chun sau y : b nhFlash 2K byte , 128 byteRAM , 15 ng I/O, 2 bnh thi/m 16-bit , kin trc ngt hai mc 5 vector, port ni tiphon ton song cng , mch so snh tng t chnh xc, mch dao ng v to xung clock trnchip . Ngoi ra AT89C2051 c thit k c mch logic tnh cho hot ng gim n tn s 0Hz v h tr2 ch tit kim cng sut la chn c bng phn mm.

Ch d ngh( idle mode ) s dng CPU nhng vn cho php RAM, cc bnhthi/m, port ni tip v h thng ngt tip tc hot ng. Ch gim cng sut duy tr nidung ca RAM nhng lm dng mch dao ng, khng cho php mi chc nng khc ca chiphot ng cho n ln reset cng k tip (ngha l ta thit lp li trng thi ban u [reset] cho

chiop bng mch in bn ngoi).


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I.3 CU HNH CHN

Hnh 1.1

I.4 S KHI


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Hnh 1.2

RAM ADDR. REGISTER: thanh ghi a ch RAM .RAM: vng nhtruy cp ngu nhin (RAM).FLASH: vng nhFLASH.B REGISTER:thanh ghi B.ACC: thanh cha.STACK POINTER: con tr vng nhxp chng.PROGRAM ADDRESS REGISTER: thanh ghi a ch chng trnh.TMP1: thanh ghi tm 1TMP2: thanh ghi tm 2ALU: n v s hc/logic.BUFFER: bm.PC INCREMENTER: b tng thanh ghi m chng trnh PC.INTERRUPT, SERIAL PORT AND TIMER BLOCKS: cc khi ngt, port ni tip

v nh thi.PROGRAM COUNTER: bm chng trnh PC.PSW: t trng thi chng trnh .

TIMING AND CONTROL:mch logic iu khin v nh thi.INSTRUCTION REGISTERED: thanh ghi lnh.DPTR: con tr d liu .PORT1 LATCH: b cht port 1.PORT3 LATCH: b cht port 3.ANALOG COMPARTOR:b so snh tng t .OSC:mch dao ng.PORT 1 DRIVERS: cc mch kch port 1.PORT 3 DRIVERS: cc mch kch port 3.

I.5 M T CHNVCC

Chn cp in p Vcc cho chip.GNDChn ni t.

Port 1Port 1 l port I/O (port nhp/xut: input/output port) hai chiu 8-bit. Cc chn ca port t

P1.2 n P1.7 cung cp cc mch ko ln bn trong (internal pull-ups). Cc chn P1.0 v P1.1yu cu cc mch ko ln bn ngoi . P1.0 v P1.1 cng cn c s dng lm ng vo dng(AIN0) v ng vo m (IN), theo th t, ca mch so snh tng t chnh xc trn chip (on chip precision analog comparator).

Cc mch m ng ra (output buffer) ca port 1 c th ht dng 20mA v kch trc tipcc b hin th LED. Khi cc logic 1 c ghi n cc chn ca port 1, cc chn ny c thcs dng lm cc ng vo. Khi cc chn t P1.2 n P1.7 c s dng lm cc ng vo v c

ko xung mc thp t bn ngoi, chng s cung cp dng (IIL) do cc mch ko ln bn trong.Port 1 cng nhn d liu chng trnh hay d kiu m (code data) trong thi gian lp trnh

v kim tra b nhFlash.Port 3

Cc chn ca port 3 t P3.0 n P3.5, P3.7 l chn I/O hai chiu vi cc mch ko ln bntrong. P3.6 c ni dy cng lm ng vo ni n ng ra ca mch so snh trn chip v khngth truy cp nh mt chn I/O c mc ch tng qut. Cc mch m ng ra ca port 3 c th htdng 20mA.Khi cc logc c ghi n cc chn ca port 3, cc chn ny c ko ln mc cao

bi cc mch ko ln bn trong v c thc s dng lm cc ng vo. Khi l cc ng vo, ccchn no ca port 3 c ko xung mc thp bi mch bn ngoi s cung cp dng (IIL) do cc


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mch ko ln. Cc chn ca port 3 cn c s dng cho cc chc nng c bit khc caAT89C2051 nhc lit k di y ( bng 11,1). Port 3 cng nhn mt s tn hiu iu khin lp trnh v kim tra b nhFlash.

Bng 1.1RST

Ng vo reset (thit lp li trng thi ban u). Tt c cc chn I/O c reset n mclogc ngay sau khi RST ln mc cao. Vic duy tr chn RST mc cao trong 2 chu k my trongkhi mch dao ng ang hot ng s reset chip.

XTAL 1

Ng vo n mch khuch i dao ng o v ng vo n mch to xung clock bntrong.

XTAL 2Ng ra t mch khuch i dao ng o.

I.6 CC C TNH CA MCH DAO NG.

XTAL 1 v XTAL 2 l ng vo v ng ra, theo th t, camch khuch i o c thc cu hnh trthnh mch daong trn chip nhc trnh by hnh 1.3. Mt tinh th thchanh hoc mch cng hng gm u c th s dng c. kchchip t ngunxung clock bn ngoi, chn XTAL 2 s khng ktni trong khi chn ATAL 1 c kch nhc trnh by hnh1.4. Khng c yu cu no v chu k nhim v (duty cycle) catn hiu xung clock bn ngoi v ng vo n mch v ng vo nmch to xung clock bn trong si qua mt flipflop lm nhimv chia 2 tn s, nhng cc c tnh vin p ti thiu v ti aca mc cao v mc thp phi c xem xt.Hnh 1.3 cc kt ni ca mch dao ng.

Lu : C1,C2=30pF 10pF i vi cc thch anh ; C1,C2=40pF 10pF i vi cc bcng hng gm.

Hnh 1.4: Cu hnh kch xung clock bn ngoi.


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I.7CC THANH GHI CHC NNG C BIT SFR

Bng 1.2 Cc gi tr khi reset v bn cc SFR ca AT89C2051Mt bn vng nhtrn chip c gi l khng gian thanh ghi chc nng c bit SFR

(special function registor) c trnh by bn trn y (bng 1.2). Lu rng khng phi tt c

a chu b chim bi cc thanh ghi ny, cc a ch khng b chim c th khng c thchin trn chip. Cc truy cp c n cc a ch ny trong trng hp tng qut, s tr v d liungu nhin v cc truy cp ghi s c tc ng khng r rng.

Phn mm ca ngi s dng khng nn ghi cc logic 1 n cc v tr nhkhng c litk v chng c thc s dng trong cc sn phm tng lai p ng cc t tnh mi.Trong trng hp , cc gi tr do reset hoc cc gi tr khng tch cc ca cc bit mi s lunlun bng 0.

I.8 CC GII HN TRN MT S LNH

AT89C2051 l mt thnh vin tit kim v c hiu qu v gi thnh ca h vi iu khinang pht trin ca Atmel. Chip ny cha 2K b nhchng trnh Flash. Chip ny hon tontng thch vi kin trc MCS-51v c thc lp trnh bng cch s dng tp lnh MCS-51.tuy nhin, c vi cn nhc m ta ohi ch khi s dng mt s lp trnh ca chip ny.Tt c cc lnh lin quan n cc hot ng nhy v r nhnh s b gii hn, chn hn nhachh ri vo trong khng gian nhca chip, khng gian ny l 2K byte vi AT89C2051. Vn ny l trch nhim ca nguowif lp trnh phn mm.Th d, lnh LJMP 7E0H s l lnh hp li vi AT89C2051 (c 2K byte b nhchngtrnh)trong khi lnh LJMP 900H l lnh khng hp l.


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Cc lnh r nhnhLCALL,LMJP, ACALL, AJMP,SJMP ,JMP@A+DPTR- Cc lnh r nhnh khng iu

kin ny s thc thi ng min l ngi lp trnh lu rng a chch r nhnh phi nm tronggii hn vt l ca kch thc b nhchng trnh (cc v tr nht 00H n 7FFH i viAT89C2051). Vic vi phm cc gii hn khong gian vt l c th gy ra hnh vi khng bitc ca chng trnh

CJNE [. . . ], DJNZ [. . . ], JB, JNB, JC, JNC, JBC, JZ, JNZ - Vi cc lnh r nhnh ciu kin ny, cc quy lut ging nhtrn cng c p dng. Mt ln na, vic vi phm ccgiis hn b nhvt l s lm cho chng trnh thc hti khng ng.i vi cc ng dng bao gm cc cch ngt, cc v tr a ch ca chng trnh phc v ngt(interrupt service rountine) bnh thng ca cu trc h 89C2051 c bo ton.

Cc lnh lin quan n MOVX, b nhdliuAT89C2051 cha 128 byte b nhd liu bn trong (intenal data memory). Nh vy

trong AT89C2051,kch thc ca b xp chng (stack depth) c gii hn ti 128 byte, ay ldung lng ca RAM c sn. Vic truy cp b nhbn ngoi khng c h trtrong chip nyv vic thc thi chng trnh bn ngoi cng khng c h tr.

Nh vy khng c lnh MOVX [. . . ] no cha trong chng trnh.Mt trnh dch hp ng (assembler) in hnh ca 89C51 vn dch cc lnh ny,ngay c

khi chng c vit di dng vi phm cc gii hn cp trn. Ngi s dng b vi iukhin phi c trch nhim phi bit cc tnh cht vt l v gii hn ca linh kin ang c sdng v iu chnh cc lnh c s dng mt cch thch hp.

Cc gii hn trn y cho ta thy cc khuyt im ca At89C2051.I.9 CC BIT KHO B NHCHNG TRNH

Vi chip AT89C2051 ta c 2 bit kho (lock bit), cc bit ny c th li khng lp trnh(U) hoc c th lp trnh (P) nhn thm c cc tnh cht c lit k bng 11.3.

Cc bit kho chng trnhLB1 LB2

Loi bo v

1 U U Khng c tnh cht kho chng trnh.

2 P U Vic lp trnh thm na cho b nhFlash b cm.3 U U Tng t ch 2, vic kim tra cng b cm.

Lu : cc bit kho ch c th b xo bng thao tc xo chipBng 1.3:Cc ch bo v ca bit kho.

I.10 CH NGH

Trong ch ngh CPU s t ng, trong khi tt c cc ngoi vi khc trn chip iu hotng v iu duy tr trng thi ch tch cc. Ch ny c yu cu bi phn mm. Nidung ca RAM trn chip v tt c tren cc thanh ghi chc nng c bit iu gi nguyn khngthay i trong thi gian ch ny. Ch ngh c thc kt thc bi cch ngt bt k c

php hoc bng cch reset phn cng.Cc chn P1.0 v P1.1 sc thit lp bng 0 nu khng sdng cc mch ko ln

bn ngoi hoc c thit lp bng 1 nu c mch ko ln bn ngoi.Cng cn lu rng khi ch nghc kt thc bi mt reset cng, chip s tip tc

thc thi chng trnh bnh thng t ni chng trnh b ri b, n 2 chu k my trc giithut reset bn trong ly quyn iu khin. Phn cng trn chip ngm cn vic truy cp nRAM bn trong ch ny nhng khng cm vic truy cp n c chn ca port. lai bkh nng c mt thao tc khng mong i n mt chn ca port khi ch nghc kt thc

bng reset, lnh theo sau lnh yu cu ch ngh s khng th l lnh ghi n mt chn port hocb nhngoi.


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I.11CH GIM CNG SUTTrong ch gim cng sut, mch dao ng b dng v lnh yu cu ch gim cng

sut l lnh sau cng c thc thi. RAM trn chip v cc thanh ghi chc nng c bit gi licc gi tr ca chng cho n khi cc ch gim cng sut c kt thc.Li thot duy nht rakhi ch gim cng sut l s dng reset cng. Reset snh ngha li cc thanh ghi chua\cnng c bit nhng khng lm thay i Ram trn chip. Reset khng nn c kch hot trckhi in p VCC c khi phc n mc hot ng bnh thng v reset phi duy tr tch cc lu cho php mch hot ng trli v trnn n nh.Cc chn P1.0 v P1.1 sc thit lp bng 0 nu khng sdng cc mch ko ln bnngoi hoc c thit lp bng 1 nu c mch ko ln bn ngoi.

I.12 LP TRNH FLASHAT89C2051 trn th trng c di nhchng trnh PEROM trn chip la 2K byte

trng thi c xa (ngha l ton b ni dung ca cc byte l FFH) v sn sng c lptrnh. Di nhchng trnh c lp trnh mt byte cho mi thi im.Mt khi di ny clp trnh, lp trnh li bt k byte no khng trng, ton b di nhc xa bngin.

Bim a ch bn trongAT89C2051 c mt bm a ch PEROM bn trong, bm ny lun lun c thit

lp l 00H cnh ln ca RST v c tng ln bng cch p dng xung ang trthnh mcdng (positve going pluse) n chn XTAL1.Gii thut chng trnh

lp trnh AT89C2051, theo trnh t sau y.1. Trnh t cp in:

Cp in gia cc chn VCC v GNDThit lp RST v XTLA1 n mc thp (GND)

2. Thit lp RST ln mc cao (H)Thit lp chn P3.2 ln mc cao (H)

3. p dng t hp cc mc logic H v L thch hp n cc chn P3.3, P3.4, P3.5 v P3.7 chn 1 trong cc thao tc lp trnh c trnh by trong bng cc ch lp trnh PEROM(PEROM proramming modes table).

lp trnh v kim tra di nhchng trnh:4. t d liu ca byte chhng trnh ( hay cn gi l byte m) v tr 00h n cc chn t P1.0n P1.7.5. Tng RST ln 12V cho php lp trnh.6. a mt xung n chn P3.2 lp trnh mt byte trong di PEROM hoc cc bit kha. Chuk ghi byte c tnh thi v in hnh chim 1.2ms.7. kim tra d liu lp trnh, gim thp RST t 12V xung mc logic cao H v thit lpcc chn t P3.3 n P3.7 n cc mc logic thch hp. D liu xut c thc c cc chnca port 1.8. lp trnh mt byte v tr a ch k tip, a mt xung n XTAL1 tng bm ach bn trong (internal address counter). t d liu mi n cc chn ca port 1.9. Lp li cc bc t 6 n 8, thay i d liu v tng bm a ch cho ton b di byte

hoc cho n khi kt thc tp tin i tng (object file).10.Trnh t ngt ngun in.

Thit lp XTLA1 n mc thp (L)Thit lp RST n mc thp (L)Tt ngun cp in cho VCC.


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DataPolling: AT89C2051 c Data Polling ch ra vic kt thc mt chu k ghi.Trong thi gian ca mt chu k ghi, vic thc byte sau cng c ghi s dn n vic ly bd liu c ghi trn chn P1.7. Mt khi chu k ghi kt thc, d liu s c hiu lc trn tt c

cc ng ra v chu k k tip c th bt u. Data Polling c th bt u bt c lc no sau khkimt chu k ghi c khi ng.

Ready/ Busy : Tin trnh lp trnh byte cng c th gim st bng tn hiu ng ra RDY/

BSY . Chn P3.1 c ko xung mc thp sau khi chn P3.2 trthnh mc cao trong thi gianlp trnh s ch ra trng thi bn (BUSY).

Chn P3.1 c ko ln mc cao ln na khi vic lp trnh kt thc s chh ra trng thisn sng (READY).

Program verify ( kim tra chong trnh ): Nu cc bit kha LB1 v LB2 khng clp trnh, d liu chng trnh c thc ngc v thng qua cc ng d liu kim tra:1. Reset bm a ch bn trong v 00H mang RST t L ln H.2. t cc tn hiu thch hp c d liu chng trnh v c d liu ng ra cc chn ca

port 1.3. a mt xung n chn XTAL 1 tng bm a ch bn trong.4. c byte d liu k tip cc chn ca port 1.

5. Lp li cc bc 3 v 4 cho n khi ton b di nhchng trnh c c.Cc bit kha khong thc kim tra trc tip. Vic kim tra cc bit kha s nhn c bngcch tun theo cc tnh cht c cho php ca chng.

Chip erase (xa chip): Ton b di PEROM (2K byte) v hai bit kha c xa bngin bng s dng t hp thch hp cc tn hiu iu khin v bng cch gi cho chn P3.2 mc thp trong 10ms. Di nhchng trinhd c ghi vi tt c cc bit iu l 1 trong thao tcxa chip va phi c thc hin trc khi bt k byte nhkhng trng no c thc lp trnhli.

Reading the signature bytes (c cc byte ch k ): Cc byte ch k c c vi cngth tc nh vic kim tra bnh thng cc v tr nh000H, 001H, 002H, ngoi tr cc chn P3.3v chn P3.5 phi c ko xung mc logic thp. Cc gi trc tr v nh sau:

(000H) = 1EH ch ra c sn xut bi Atmel.

(001H) = 21H ch ra 89C2051.

I.13CC CH LP TRNH FLASH

Cc ch lp trnh Flash c tm tt bng 1.4.


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Lu : 1. Bm a ch PEROM bn trong c reset v 000H cnh ln ca RST v ctng bi xung dng chn XTAL 1.

2. vic xa chip yu cu xung PROG ko di 10ms.3. Chn P3.1 c ko xung mc thp trong thi gian lp trnh ch ra RDY/BSY

Write code data: ghi d liu chng trnh.Read code data: c d liu chng trnh.Write lock : ghi cc bit kha.Chip erase : xa chip.Read signature byte : c byte ch k

SEE FLASH PROGRAMMING MODE TABLE:xem bng ch lp trnh Flash.PGM DATA: d liu chng trnh.TO INCREMENT ADDRESS COUTER: tng bm a ch.

I.14 CC C IM LP TRNH FLASH

Khiu

Thng s Min Maxnv

VPP in p cho php l p trnh. 11.5 12.5 VIPP Dng in cho php l p trnh. 250 tDVGL Thi gian t lc d liu n khi PROG mc th p. 1.0 tGHDX Thi gian gi d liu sau khi PROG tch cc. 1.0 st EHSH Thi gian P3.4 ( NABLE ) t H ln VPP. 1.0 stSHGL Thi gian t lc thit lp VPPn khi PROG mc th p. 10 stGHSL Thi gian gia VPP sau khi PROG tch cc. 10 stGLGH rng ca PROG. 1 110 stELQV Thi gian t lc ENABLE mc thp cho n khi d liu c 1.0 s


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Bng 11.5 Cc t im lp trnh v kim tra Flash.TA = 0

0C n 700 C, VCC = 5.0 10%.Ch s dng ch lp trnh 12 V.

I.15 CC C LNG CC I TUYT I

Tm nhit hot ng: t -550C n +1250C.Tm nhit tch tr: t -660C n +1500C.in p trn bt k chn no so vi t (GND): -1.0 V n +7 V.

in p cp in cc i: 6.6 V.Dng DC ng ra: 25.0 mA.

CC DNG SNG LP TRNH V KIM TRA FLASH

Hnh 1.5 Cc dng sng lp trnh v kim tra Flash.

hiu lc.tEHQZ Thi gian th ni d liu sau khi ENABLE tch cc. 0 1.0 stGHBL Thi gian t khi PROG mc cao cho n khi BUSY o mc

thp.50 ns

tWC Thi gian ca chu k ghi byte. 2.0 mstBHIH Tr hon t RDY/BSY n khi clock tng. 1.0 s

tHIL Thi gian c0lockmc cao. 200 ns


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DNG SNG MCH KCH XUNG CLOCK BN NGOI

Hnh 1.6:Dng sng mch kch xung clock bn ngoi.

MCH KCH XUNG CLOCK BN NGOI

Bng 1.5 Cc thng s ca mch kch xung clock bn ngoi.

NH THI PORT NI TIP: IU KIN KIM TRA CH THANH GHI DCH

VCC = 5.0 20%; in dung ti = 80 pF.

Khiu Thng s Dao ng 12 MHZMin Max Dao ng thay iMin Max nv

Thi gian chu k xung clock portni tip.

1.0 12tCLCL s

Thi gian t lc thit lp d liuxut n cnh ln ca xung clock

700 10tCLCL 133

ns

Thi gian gi d liu xut sau cnhln ca xung clock.

50 2tCLCL 177

ns

Thi gian gi d liu nhp sau cnhln ca xung clock

0 0 ns

Thi gian t cnh ln xung clockn khi d liu nhpc hiu lc.

700 10tCLCL 133

ns

Bng 1.6 Cc iu kin kim tra chnh thi thanh ghi dch

K hiu Thng s VCC=2.7V n 6.0VMin Max

VCC=4.0V n 6.0VMin Max

n v

1/tCLCL Tn s dao ng. 0 12 0 24 MHZtCLCL Chu k xung clock. 83.3 41.6 nstCHCX Thi gian mc cao. 30 15 nstCLCX Thi gian mc th p. 30 15 tCLCH Thi gian tng (cnh ln). 20 20 nstCHCL Thi gian gim (cnh xung). 20 20 ns


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CC DNG SNG NH THI CH THANH GHI DCH

Hnh 1.7 Dng sng nh thi ch thanh ghi dch.

DNG SNG NG VO/NG RA KIM TRA AC1

Hnh 1.8:Dng sng ng vo/ng ra kim tra AC.

Lu : 1. Cc ng vo AC trong thi gian kim tra c kch (VCC 0.5) V i vi logic 1 v0.45 V i vi logic 0. Cc php o nh thi c thc hin VIHmin i vi logic 1v VILmaxi vi logic 0.

DNG SNG TH NI1

Hnh 1.9 Dng sng th ni.Timing reference points: cc im tham chiu nh thi.Lu : 1. i vi mc ch nh thi, mt chn port s khng cn th ni kho c s thay i100mV tin p trn ti. Mt chn port bt u th ni khi c s thay i 100mV t mcVOH/VOL (c ti).


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ICCCH TCH CC

Hnh 1.10: ICCch tch cc.

ICC CH NGH V CH GIM CNG SUT

Hnh 1.11: (a) ICCch ngh ,(b) ICCch gim cng sut.


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Packaging Information


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II.Gii thiu v Vi iu Khin AT89C51 MSC51 l mt h Vi iu Khin (Microcontroller) do hng Intel sn

xut.Cc IC ca h MSC51 tiu biu l 8051 v 8031. c bit, vi iukhin 89C51 sn xut gn y mang cc c im sau:

4Kbytes EEPROM. 128 bytes RAM. 4 Port I/O (Input/Output). 2 bnh thi Timer 16 bits. Giao tip ni tip. 64Kbytes khng gian b nhchng trnh mrng. 64Kbytes khng gian b nhd liu mrng. Mt b x l lun l (thao tc trn cc bits n). 210 bits c a ch ha. B nhn chia 4s.

H THNG GIAO TIP PORT. Port 0: port 0 l mt port hai chc nng trn cc chn 32-39.Hy nhrng : trn cc chn ny cha c in trko dng, do khicn chng ta cn nhn c im ny. Port 1: port 1 l mt port I/O trn cc chn 1-8. Port 2: port 2 l mt port cng dng kp trn cc chn 21-28. Port 3: port 3 l mt port cng dng kp trn cc chn 10-17. Cc

chn ny u c nhiu chc nng, cc cng dng chuyn i c linh ti cc c tnh c bit ca 8051 bng sau:


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CC TN HIU IU KHIN:Chip AT89C51 c cc tn hiu iu khin cn phi lu nh sau: Tn hiu vo EA\ trn chn 31 thng t ln mc cao ( +5V) hocmc thp (GND)

Nu mc cao, 8951 thi hnh chng trnh t ROM ni trongkhong a ch thp (4K hoc ti a 8ki vi 89C52).

Nu mc thp, chng trnh c thi hnh t b nhmrng (tia n 64Kbyte).

Ngoi ra ngi ta cn dng EA\ lm chn cp in p 12V khi lptrnh EEPROM trong 8051.

CHN PSEN (Program store enable):PSEN l chn tn hiu ra trn chn 29. N l tn hiu iu khin cho

php chng trnh mrng, PSEN thng c ni n chn OE\(Output Enable) ca mt EPROM hoc ROM cho php c cc

bytes m lnh.Hy nhrng : bnh thng chn PSEN\ sc th trng ( NoConnect).Ch khi no cho EA\ mc thp th lc :

PSEN\ smc thp trong thi gian ly lnh. Cc m nh phn cachng trnh c ly t EPROM qua bus d liu v c cht vo

thanh ghi lnh ca 8951 gii m lnh.PSEN\ mc thng (mc cao) nu thi hnh chng trnh trong

ROM ni ca 8951. CC CHN NGUN:

AT8951 hot ng ngun n +5V.Vcc c ni vo chn 40, v Vss(GND) c ni vo chn 20.


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Chng 2: Gii thiu chung v phn mm Keil Software

Phn mm Keil SoftWare 8051 cng c pht trin c lit k di l nhngchng trnh m bin tp m C, tp hp nhng tp tin assembly, lin kt v nh vnhng on chng trnh hng i tng, nhng th vin , khi to file HEX, v trnhgli.

Vision l mt mi trng pht trin tch hp m kt hp qun l project ,sontho m ngun v trnh gli trong mi trng mnh.

Cx51 ANSI ti u b bin dch C v to ra nhng on chng trnh hng itng nh v li t m ngun C.

Ax51 Macro Assembler to ra nhng an chng trnh hng i tng nh vli 8051 m ngun assembly.

BL51b kt ni / d tm nh v li nhng on chng trnh hng i tngc to ra t C51 v A51 vo nhng on chng rnh hng i tng tuyt

i. LX51 mrng b kt ni / b d tm h trnhng phng n thit b mrng vcung cp nhng c tnh b sung.LX51 h trtt c cc phng n ca Cx51 vAx51.

LIBx51trnh qunl th vin kt hp nhng on chng trnh hng i tngvo trong nhng th vin m c thc s dng bi b kt ni.

OHx51b bin i sang file HEX . to ra nhng file HEX t nhng onchng trnh hng i tng tuyt i.

RTX51 Tiny h thng thi gian thc RTX51 , thit kn gin nhng d nphn mm phc tp, nh thi.


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II.1 CHU TRNH PHT TRIN PHN MM

Khi chng ta s dng phn mm Keil Vision , chu trnh pht trin phn mmcng ging nh chu trnh pht trin bao phn mm khc.

1. Khi to project , la chn chip t csd liu thit b , thit t nhng cng cnh hnh.

2. To ra nhng tp tin ngun C hoc assembly.3. Xy dng nhng ng dng vi Project Manager.4. Kim tra li tp tin ngun.5. Kim tra nhng ng dng c lin kt.

S khi sau y minh ha chu trnh pht trin phn mm Vision/ARM y .Mi phn c m tbn di.

II.2 Vision IDE

Vision IDE kt hp qun l d n , trnh bin tp vi s sa cha li, ci t tychn, phng tin, v gip trc tuyn. S dng Vision to ra nhng tp tin ngunv t chc chng vo trong nhng d n ng dng. Vision IDE t dng bin tp, lprp, v lin kt nhng ng dng nhng.

C51 Compiler & A51 Macro Assembler (Trnh bin tp C51 v trnh hp ng A51 )

Nhng tp tin ngun c to ra bi Vision IDE v c a qua C51 hocA51.Trnh bin tp v trnh lp rp x l nhng tp tin ngun v to ra nhng tp tin itng nh v li c.


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Trnh bin dich Keil C51 l mt s thi hnh m ANSI y ca ngn ng lptrnh m h trtt c cc c tnh chun ca ngn ng C. Ngoi ra , nhiu c tnh h trtrc tip kin trc 8051 c thm.

Chng trnh Keil A51 h trtp lnh y ca 8051.

LIB51 Library Manager (trnh qun l th vin LIB51)

LIB51 cho php chng ta to ra th vin mc tiu t nhng tp tin i tng cto ra t trnh bin tp v trnh lp rp. Nhng th vin c nh dng c bit, sp tcho chng trnh nhng tp hp ca nhng on chng trnh hng i tng m cthc kt ni nhng ln sau.Khi b kt ni x l mt th vin , ch nhng onchng trnh hng i tng cn thit to ra chng trnh mi c s dng.

BL51 Linker/Locator ( B kt ni BL51/d tm)

B kt ni BL51/d tm to ra file LF/DWARF tuyt i s dng nhng onchng trnh hng i tng t nhng th vin v c to ra t trnh bin tp v trnh

lp rp.Mt tp tin i tng tuyt i hoc moun cha ng nhng m v d liukhng xc nh, Tt c cc on m v d liu hin c ti nhng v tr b nhcnh.ELF/DWARF c thc s dng

Lp trnh mt Flash Rom hoc nhng thit b b nhkhc Vi trnh gli Chng trnh chy th

Vision Debugger (Trnh gli )

Trnh gli c tnh cht tng trng, mc mc ngun gli l tng ph hp vtin cy.Trnh gli bao gm mt simulator high-speed chng ta m phng 8051.

Nhng thuc tnh ca chip m chng` ta s dng th tng nh hnh khi chng ta lachn tDevice Database. Trnh sa li cung cp vi phng php cho chng ta kimtra cc thit b phn cng

Thit t MON51 trn h thng v ti chng trnh ca bn s dng giao dinMonitor-51 ti trnh gli.

S dng giao din GDI km theo trnh gli ti h thngBn di y lit k nhng th mc cng c pht trin phn mm Keil .


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Assembler Source Template and Include files for the Macro Assembler.( file ngunassembly v nhng file cho trnh dch Macro Assembler)Executable files of the Vision/C51 tool chain.( nhng tp tin chy ca Vision/C51)Example programs ( nhng chng trnh v d)Configuration files for Flash Monitor and pre-configured versions.( Cu hnh choFlash Monitor v nhng phin bn nh hnhOn-Line documentation for Vision/C51.(ti liu trc tuyn cho Vision/C51)Include files for the C compiler.(nhng tp tin cho trnh bin tp C)Files for ISD51 In-System Debugger and pre-configured versions.(nhng file h trISD51 trnh gliRun-time libraries and CPU startup files.(th vin v CPU khi ng sp xp nhngfile)Configuration files for Monitor-51 (for Classic 8051 Devices).(cu hnh cho Monitor-51)Configuration files for Monitor-390 (for Dallas Contiguous Mode) .(cu hnh chomonitor-390)

RTX51 Tiny Version 2 Real-Time Operation System.(h thng bnh thi)

Th mc Vision


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II.3 GIAO DIN NGI DNG

II.4 Create a Procject (To mt Procject )

Vision l mt ng dng Windows v chng trnh c kch hot khi click lnbiu tng (icon)

Create a Project File (to ra mt d n)

to mt h smi ta la chn tVision menu Project New Projectmthi thoi Windows hin ra v hi bn t tn cho cho Project mi va khi to.Chnggi rng ta nn s dng mt Folder ring cho mi Project.n gin hn to mtProject mi chn biu tng to ra mt Procject mi . Vision to ra mt Procject

mi vi tn PROCJECT1.UV2 cha ng mt tn nhm v h smc nh. Ta c ththy tn ny trong Project Workspace Files .Khi ta to ra mt Procject mi uVision hi ta la chn CPU cho Procject .hp thoi

la chn thit b xut hin cho ta thy csd liu thit b uVision , ch cn la chn biu khin m ta s dng . V d nh ta chn Biu khin Philips 80C51RD+ .Nhngty chn cng c ny cho Philips 80C51RD+ c rt gn bn cu hnh cng c.


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Ch : Ta c th la chn B kt ni mrng (LX51) v trnh Assembler mrng

(AX51) trong hp thoi.Linker v Assembler mrng sn sng trong the KeilProfessional Developer's Kit v a cho chng ta nhng c tnh b sung .

Khi ta to ra mt Procject mi , uVision c th tng thm m khi ng CPU Trn mt vi thit b , mi trng uVision cn nhng tham s b sung m ta phi

thit lp.c nhng thng tin ny mt cch cn thn c cung cp di s m tca hp thoi ny, t c th c nhng ch dn b sung cho cu hnh thit b.


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Ta c th to ra mt tp tin ngun mi vi menu option File New. iu ny mmt ca s bin tp, ni m ta c th bin son m ngun. uVision nhng c php mukhi ta lu file vi hp thoi (File Save As) di tn *.C. V d chng ta lu di tnMain.C

Khi ta to tp tin ngun , ta c th thm file ti Procject . Nhng xutuVision vi cch thm tp tin ngunvo mt Procject. V d nh ta c th la chnnhm Procject Workspace-Files v click chut phi mmenu. Ty chn Add filesc mra. Chn file MAIN.C m ta to ra.


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Thm v nh hnh m khi ng ( Add and Configure the Starup Code)

File STARUP.A51 l m khi ng cho a s CPU 8051. M khi ng lm sch bnhd liu v to nhng con tr ngn xp. Ngoi ra mt vi dn xut 8051 yu cu mtm khi to CPU ph hp vi vi cu hnh phn cng. V d Philips 8051RD+ ngh tachn on-chip xdata RAM m cn c thm vo trong m khi ng. Khi ta cn sa i

file ton hc cho ph hp vi phn cng, ta phi copy file STARUP.A51 tC:\KEIL\C51\LIB n ngn Procject

To nhm Procject

Nhm h scho php chng ta t chc nhng Procject ln. Cho m khi ngCPU v nhng cu hnh h thng m ta c th to ra mt Procject nhng thnh phn,mi trng , hng dn trong hp thoi.Chn mt group mi to ra mt h thng ctn nhm h sngn xp. trong Procject mi c th ko th file STARTUP.A51 lnnhm file mi ny.

By gi, Project Workspace Files lit k tt c trong Project . mmtProject son tho, nhn double ln file Project Workspace .Ta c th cn nh hnhSTARTUP.A51 trong trnh bin tp.


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Thit t nhng ty chn cho nhng mc tiu.

uVision cho chng ta thit t nhng ty chn cho mc tiu phn cng .Hp thoinhng ty chn cho nhng mc tiu c mqua biu tng thanh cng c hoc quamenu ty chn Project. Trong bng mc tiu ch r nhng tham s thch ng phn cngv thnh phn chip m bn la chn. Sau y l v d nhng thit t :

Sau y l bn m t nhng ty chn ca hp thoi Target


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Xtal ch tn s clock m CPU ca bn hot ng. Trong a s trng hp gi tr nyng nht vi tn s XTAL.( Specifies the CPU clock of your device. In most casesthis value is identical with the XTAL frequency)Memory Model ch r b nhC51, bt u nhng ng dng mc nh l mt s lachn tt.Allocate On-Chip...

Use multiple DPTR registers ch r cch dng nhng thnh phn ca chip cho phpm khi ng CPU , nu ta ang s dng b nh xdata RAM ta cng phi cho php struy nhp XRAM trong STARTUP.A51 sp xp.Off-chip...Memory ch r tt c cc vng b nhngoiCh r nhng tham s cho m v xdata. Tham chiu ti Code Banking bit thm chitit hn Specifies the parameters for code and xdata banking. Refer to the "CodeBanking" section for more information

Vi ty chn trong hp thoi ch c nu ta ang s dng LX51 Linker/Locater.LX51 Linker/Locater ch c trong gi PK51

Xy dng Project v khi to file HEX

Nhng thit t cng c di nhng ty chn-mc tiu m ta cn khi ngmt ng dng mi. Ta c th dch tt c cc tp tin ngun v k nhng ng dng vi mtci click trn biu tng Build Target . Khi ta xy dng vi nhng li c php, uVisions trnh by nhng thng bo li v cnh bo vi nhng li c th xy ra. Nhn doubletrn hng thng bo li mfile ngun nh v trong trnh bin tp uVision

Mt ln thnh cng ta c th khi ng trnh gli nh m t di TestingPrograms vi trnh gli uVision .


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By gita c th sa li m ngun hoc thm nhng tp tin ngun mi vo d n.Nt thanh cng c Build Target dch nhng file ngun chc sa i, hoc file ngunmi v file thc thi. uVision lu gi mt danh sch v nhng file c s dng trong filengun. Thm ch nhng ty chn cng cc lu tr trong danh sch ph thuc, uVision xy dng li nu cn thit, vi lnh Rebuild Target , tt c nhng file ngunc dch bt chp nhng ci bin.

Sau khi kim tra ng dng ca bn, n c th yu cu to ra file HEX v tixung phn mm ng dng vo trong thit b s dng mt tin ch lp trnh Flash.uVision to file HEX vi mi ln xy dng di nhng ty chn cho Target-Outout dccho php. Ty chn Merge32K Hexfile sn sng cho nhng ng dng Code Applocationskhi ta la chn Extended Linker LX51. Ta c th khi ng tin ch lp trnh Flashsau khi trnh dch lm qu trnh khi bn ch r nhng chng trnh Run Program#1.


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Chng trnh muMc ny m t nhng chng trnh mu chy trn Keil C51. Nhng chng trnh

mu ny sn sng cho bn chy th. Nhng chng trnh ny gip ta hc cch s dngcc cng c ca Keil C51. ng thi, ta cng c th sao chp cc an m ca chng vochng trnh ca chng ta.

Cc chng trnh mu ca Keil C51 c lu trong thu mc

C:\KEIL\C51\EXAMPLES\ . Mi chng trnh c lu trong mt th mc ring cngvi mt tp tin d kin gip bn c th nhanh chng xy dng v nh gi chng trnh.Ngoi ra, cc chng trnh nh ring bit cho RTX 51 cng c cung cp trong

mc RTX 51.Bng sau l danh sch cc chng trnh mu trong C51 v tn th mc ca chng.Kiu mu M t

ADI 83x Cc chng trnh dng cho cc thit b tng t ADuC83x vADuC84x m n ch ra cc thit b mrng v cch dng ADIMONITOR DRIVER

ASM Mt chogn trnh hp ngn gin m ta c th vit mt ontext cho cc port tun t

Benchmarks\... Vi chng trnh ring bit: Dhrystone, Whetstone, Sieve.BLINKY Loi 8051 Blinky lm sng LED trn board Keil MCBx51CodeBanking\... Kiu m Banking ch ra vic lp trnh trn b nh64KCSAMPLE B cng v trn gin m cho thy lm sao xy dng mt

chng trnh vi nhiu module trn VisionDallas 390 Vi v d s dng Dallas Contigious Addressing Mode m n c

sn mt vi thit b khc nhau nh DS80C390, DS80C400,DS80C41x, DS5240, and DS5250.

FarMemory Lm sao mrng nhtr6n 64KHello Chng trnh hin ch Hello world. Chy th n trc khi s

dng Vision.Infineon C517 Cho thy cch dng Infineon mrn cc thit b: MDU v bgiao in ni tip.

Infineon XC866 Nhng chng trnh mu cho bo mch Keil MCBXC866 h trc thit b Infineon XC800

M8051EW Cc chng trnh mu cho Mentor M8051EWMEASURE L h thng thu thp v tp hp nhng d liu s v tng t. L

chng trnh iu khin h thng o lng nhit t xa.Philips 80C51MX L chng trnh mu cho h Philips 80C51MX h trti 16MB

vng a chPhilips LPC9xx Chng trnh cho bo mch Keil MCB900 Evaluation m h tr

cc thit b Philips LPC900 - LPC94xPhilips LPC95x Chng trnh cho bo mch Keil MCB9xx Evaluation m h tr

cc thit b Philips LPC950 - LPC99xST uPSD Chng trnh mu cho dng ST uPSD cho thy cu hnh h

thng Keil ULINK USB-JTAG AdapterTI MSC121x Chng trnh cho cc thit b TI MSC121x ch ra cch dng h

thng gii m ISD51 In-System DebuggerTI MSC1200 Chng trnh cho cc thit b TI MSC1200 ch ra cch dng h

thng gii m ISD51 In-System Debugger


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bt u s dng mt trong cc chng trnh mu, ta mmenu Project Open

Project trong Vision ri mtp tin chng trnh.Cc mc trong chng ny m t lm sao s dng cc cng c xy dng cc

chng trnh sau: HELLO : chng trnh C vit cho 8051 MEASURE: h thng o lng t xa.HELLO

Chng trnh HELLO c lu trong th mcC:\KEIL\C51\EXAMPLES\HELLO\ .chng trnh ny khng lm g hn l

xut on text HELLO WORLD ra port. Ton b chng trnh c lu trong tp tinngun l HELLO.C

ng dng nh ny gip bn c th bin tp, lin kt v gli mt ng dng. Bnc th thc hin thao tc ny t dng lnh trn DOS, s dng tp tin dng batch hocdng Vison trn windown vi cc tp tin chng trnh.

Phn cng cho ch HELLO da vo CPU 8051 chun. Mt con chip ngoi vic s dng cho cc dy port. Tuy nhin, vi Vision bn khng cn phi c 1 CPU v

chng trnh ng vai tr phn cng yu cu cho chng trnh ny.Tp tin chng trnh HELLO

Trong Vision, nhng ng dng c lu trong tp tin chng trnh. Mt chngtrnh c vit cho ch HELLO. mchng trnh ny ta chn Open Project t menuProject v mtp tin HELLO.UV2 t th mc \C51\EXEMPLES\HELLO.

Son tho chng trnh HELLO.CBy gibn c th son tho chng trnh HELLO.C bng cch nhp p chut

vo ca s project file. Vision s ti v hin th ni dung file HELLO.C trn ca s lmvic.


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Bin dch v kt ni HELLOKhi bn sn sng bin dch v lin kt chng trnh ca mnh, s dng lnh BuildTarget t menu Project hot thanh cng c Build. Vision bt u bin dch v lin ktto ra mt on chng trnh m bn c th ti vo Vision cho vic th li. Qu trnhxy dng c lit k trong ca s ng ra.

Ch Bn cn phi khng gp li khi chy cc chng trnh mu

chy thHELLOKhi chng trnh HELLO c bin dch v kt ni ta c th kim tra n vitrnh tm li ca Vision. Trong Vision, s dng lnh Start/Stop Debug Session tmenu Debug hoc thanh cng c. Vision khi to trnh bo li v khi ng ccchng trnh con n cc chng trnh chnh. Sau y l mn hnh hin th:


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Mca sSerial Window #1 cho ta thy cc hin thng ra vi lnh mca sSerial Window #1 t menu VIEW hoc thanh cng cDebug.

Chy chng trnh HELLO vi lnh GO t thanh cng cDebug. Chngtrnh li cho c thc hin v hin thon vn bn HELLO WORLD trong ca sserial window. Sau khi ng ra hin th HELLO WORLD n s chy vi vng lp vtn.

Dng vic chy chng trnh HELLO vi lnh Halt t menu Debug hocthanh cng c. Bn cng c thnh lnh ESC trong trang lnh ca ca sOUTPUT.

Trong sut qu trnh kim tra li ca Vision sc hin th nh sau:


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Chy tng bc v ngt ngang

S dng lnh Insert/Remove Breakpoints t thanh cng c hoc t trnhn trn menu lp trnh. Ta dng chut phi t im dng trn im bt u ca hinchnh.

S dng lnh Reset CPU t menu DEBUG hoc thanh cng c. Nu bn

dng chng trnh ang chy bi lnh RUN. Vision s dng chng trnh ti imdng m bn t.

Bn c th chy tng bc chng trnh HELLO bng cch n nt STEP trnthanh cng c DEBUG. Nhng cu lnh sc ch ra vi mt tn mu vng. Mi tn sdi chuyn theo tng bc thc hin.

t con tr chut trn cc bin xem gi tr ca chng.

Bn c th chy hoc dng chng trnh bt k kc no vi lnhSTART/STOP DEBUG.

MEASURE: h thng iu khin thit b txaChng trnh iu khin (MEASURE) c lu trong th mc

..\C51\Examples\Measure. Chng trnh ny s dng cc d liu s v tng t thngc dng trong cc i kh tng v iu khin trong cng nghip.

Chng trnh ny chy trn P89LPC935 CPU v ghi d liu t hai port k thut sv bn ng vo chuyn i A/D. Mt bnh thi (Timer) iu khin qu trnh ly dliu. Mu d liu c thnh hnh t 1 mili giy n 60 pht. Mi d liu o c trongsut thi gian hoc t cc knh ng vo c lu vo RAM.


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Tp tin lnh ca chng trnh o lngTp tin ny c tn l MEASURE.UV2. mtp tin ta dng lnh Open Project

t menu Project v chc file MEASURE.UV2 trong th mcC:\Keil\C51\Examples\Measure.

Trang tp tin trong ca s Project cho ta thy nhng tp tin ngun dng binson chng trnh trc lng. Chng trnh o lng mu gm c 3 tp tin ngun l:

Getline.c, Mcommand.c, v Measure.c m ta c th tm thy trong nhm file ngun.Ngoi ra bn cn c th tm thy m khi ng CPU v tp tin d liu. mmt file ta nhp p vo tn tp tin trong Project Workpage

Cc chng trnh c chc nng nhm vo cc mc ch khc nhau cho nhng mitrng th nghim khc nhau. d li chy chng trnh m phng ta chn mc m

phng SIMULATOR trong thanh cng c BUILD. Khi s dng phin bn c lngEvaluation Version bn cn phi chn Demo - Simulator.


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M t cc chc nng ca tp tin ngun

Measure.c Chc cc hm chnh ca C cho h thng o lng viu kin ngt cho timer0. cc hm chnh khi to ttc cc thit b ngoi vi ca P89LPC935 v x l cclnh h thng. iu kin ngt timer,timer0, qun l

ng h thi gian thc v ly d liu t php o cah thng.

Mcommand.c Nhng qu trnh hin th, thi gian v khong cchgia cc lnh. Nhng hm ny c gi t chngtrnh chnh. Cc lnh hin th gi tr tng t timgiao ng s cho tn hiu in t 0.00V n 3.30V

Getline.c Gm cc dng lnh c son tho cho nhng dkin nhn t cc port

Yu cu phn cng

Cc ng dng o lng ch c th chy trn bo mch Keil MCB900 hoc cc phncng cbn khc dng P89LBC935. B vi iu khin PL89LBC935 cung cp kh nngnhp vo c tn hiu s v tng t. Port 1 v Port2 c dng nhp tn hiu s v tAD00 n AD03 nhp tn hiu tng t.

Tuy nhin, chng ta s khng cn mt bo mch no ht v Vision tch hpchc nng ny.

bin dch v lin kt chng trnh MEASURE

Khi sn sng bin dch v lin kt chng trnh, s dng lnh Buil Target tmenu Project hoc thanh cng c. Vision s thc hin ton b qu trnh v s thng bo

cho bn khi hon tt.

chy thchng trnh MEASURE

Chng trnh mu iu khin o lng c lp trnh chp nhn cc lnh trnchip ca cc port tun t. Nu bn c phn cng thc t, bn c th d dng phn m

phng cui cng kt ni vi CPU P89LPC935. nu bn khng c phn cng th cth s dng phn cng m phng trn Vision. Bn c th s dng ca s SerialWindown cung cp tn hiu c nhp vo.


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Mi ln chng trnh Measure c xy dng bn c th chy th. S dng lnhSTART/STOP trong menu DEBUG chy chng trnh kim tra li.

Nhng lnh ca h thng iu khin o lng txa

Chui cc lnh dng cho chng trnh c lit k trong bng. Nhng lnh nybao gm bng m ASCII v tt c cc lnh iu phi c hon tt bng mt s quay

vng.Lnh Cu trc Chc nng

clear C Xa tt c cc d liu o c trc

Dislay D Hin th thi gian lm vic v gi tr ngvo

time T hh:mm:ss t thi gian theo chun 24h

Interval I mm:ss.ttt t nhng khong thi gian cho mi phpo khong thi gian ny t 0:00.001(1ms)

v 60:00.000 (60 pht)

start S Khi ng qu trnh ghi d liu o c.Khi nhn lnh start, chng trnh o lymu tt c cc tn hiu ng vo ti cckhong thi gian nh.

Read R[count] Hin th cc gi tro c, bn c th chr s ca t1t c cc mu m mnh munc. Nu khng ch ra th t no, lnh cs hin th tt c cc gi tro. Bn ch c

thc cc gi tr ny trong 1 giy. Numun hn th phi dng chng trnh.

quit Q Thot khi qu trnh ghi gi tro

Khi bn chy mt ln chng trnh m phng trn Vision, bn c th vo cclnh ny trong ca sSerial Windown#1 bn di:


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Hin th cc on m ca chng trnhVision cho php bn hin th cc on m ca chng trnh trong ca s

Disassembly Window bng cch mmenu View hoc dng cc nt trn thanh cng c.Ca sDisassembly Window cho thy s trn ln cc ngun v cc on assembly. Bnc th thay i cch hin th bng cch nhp chut phi vo menu ng cnh.


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hin th ni dung cc nhVision c th hin th cc nhcc nh dng khc nhau. Ca s nh

Memory Window c mt menu View hoc t thanh cng c. Bn c th nhp ach ca 4 vng nh trang ny. Menu ng cnh cho php bn sa i ni dung nhhoc la chn nhng kiu ng ra khc nhau.

cc bin thay i ng h thi gian

Bn c th lin tc nhn ni dung ca cc bin, cu trc v cc mng. Ta c th mca sWatch Window t menu View hoc thanh cng c. Mt trang ng cnh hin racho thy taa61t c cc k t ng cnh ca hm hin thi. Cc trang Watch#1 v Watch#2cho php ta vo bt k bin no ca chng trnh nhtrang sau:

Vo cc bin thi gian trong ca sWatch WindowLa chn vn bn < n F2 chnh sa > cng vi 1 ci click chut v i trong

mt giy. Mt ci click chut khc cng qu trnh chnh sa gip ta thm vog a tr cacc bin. Vi cng cch nh trn ta c th thay i nhiu gi tr. Cch khc l bn c thdng phm F2.


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phn

bnsut

menu

n Tt Nghi

xa iNhng c

chiu s lCh Ca s Wchu trnh chVo binChc mt

ng cnh

Vo ccS dng l

p

mt bin,u trc v m

g nhau.

atch Windiew - Periy chngthi gianbin trongng cch c

in thi gnh Watch

h n chnng s hi

w cp nhdic Wind

trnh m p

ca s svng sonlick phi c

an ttranSet th

n phmra khi n

bt c khw Updateng.

on thotho v dut.

g lnh nggi tr bi

delete. hiu [+].

i no chcc gi tr

g cu lnh

ra (outpun vo ca

Cc dng

g trnh thcp nht s

Add to

window) Watch

b tht vo

c hin dnly lin t

atch Win

indow

. Khi

c trong

ow t


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Thc hin chng trnh

trc khi bt u m phng chng trnh MEASURE, mca sSerialWindow#1 hin th chui gi tr ng ra bng cch vo menu View hoc thanh Debug.Bn c th thu nh cc ca s khc nu mn hnh khng ln. Bn c th chy tng

bc bng lnh Step cc cu lnh Essembler hoc cc on m gc. Nu ca sAssembly Window ang m, bn nn chc chy tng bc cc lnh essembly cbn.

Nu ca s son tho vi cc m gc c m, bn chy tng bc vi tng m ngun.

nt lnh chy tng bc n (stepinto) cho php bn thc hin mt bcnhy n cc chng trnh c gi

thc hin vic gi mt hm v s khng tng ngt cho n khi gp imngt.

trn nguyn tc ta c th ngu nhin nhy vo mt hm cha hon tt. Bn cth dng lnh StepOut hon tt hm v tr li gi tr cho n ngay lp tc khi clnh gi.

mi tn vng nh du cu lnh hin thi v hoc cc lnh cp cao. Bn c thngu nhin bc vo mt hm cha hon tt.

lnh chy ngay hng ca con tr (Run till Cursor Line)

lnh t v bim ngt Insert/Remove BreakPointHp thoi BreakPointvision cng h trcc im ngt phc tp. Chng hn bn mun ngt mt

chng trnh khi mt bin t gi tr nht nh. Ci t bn di khi no gi tr 3 cvit cho current.time.sec


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nh ngha im dng ny ta mhp thoi BreakPoint t menu Debug. nhdu chn vo Write ( du chn ny ch ra l lnh ngt chc kim tra khi c vitti ). Tip tc click vo nt Define chn im dng. kim tra vic thc hin imdng lm cc bc sau:

Reset CPU

Nu s thc hin chng trnh dng th bt u chy chng trnh o

Sau mt t thi gian, Vision dng s thc hin. Chng trnh m hng nhdu v tr hng m trong im ngt c t.

Sghi vt tinQu trnh ny thc hin trong sut thi gian kim li cho n im dng ni bn

yu cu thng tin cho gi tr thanh ghi v nhng nguyn nhn khc dn ti d ngt. NuDebug - Enable/Disable Trace Recording c t bn c th nhn thy cc lnh linquan ti CPU thc hin trc im dng.


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Bng gi tr cc thanh ghi

Gi ngn xpCc ngn xp trong ca Vision sc lp y khi chng trnh hon tt. Trang

CallStack ca ca s Watch Window cho thy s lng nhau gia cc hm hin thi. Nhpp ln mt hng hin th m gc thc hin chc nng ca n.

On-Chip ngoi viVision cung cp mt s cch hin th v sa di cc chip ngoi vi s dng

trong chng trnh ca bn. Bn c th thy kt qu ca v d khi thc hin cc bc sau:

Reset CPU v xa tt c cc im ngt

Nu chng trnh b dng khi bt u o lng.

Mca s Serial Window #1 v vo lnh d cho ng dng MEASURE.Chng trnh o lng cho thy gi tr t ng vo port1 v port2 v b chuyn i A/D1-3. Ca s Serial Window #1 c biu din hnh sau:


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Nhng hp thoi thit b ngoi viVision cung cp cc hp thoi cho: I/O port, thit b ngt, bnh thi, chuyn

i A/D, v mt s chip ngoi vi c bit. Cc hp thoi ny c th mt menuPeripheral. Mi hp thoi cho thy cc k hiu SFR lin quan v tnh trng cc thit bngoi vi.

Cho ng dng o c bn c th mPeripherals - I/O Ports - Port2 vPeripherals - A/D Converter - ADC0/DAC0. nhng hp thoi ny cho thy tnh trngca cc thit b ngoi vi v bn c th thay i gi tr ng vo.


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Bn c th s dng Virtual Simulator Registers (VTREGs) thay i gi tr ngvo. Trong ca s Output Window Command Page bn c tht cc n nh cho cck hiu VTREG ging nh ngng bin v cc thanh ghi.

V D:PORT2=0xDA ; set digital input PORT2 to 0xDA.

AD01=2.3 ; set analog input AD01 to 2.3 volts.

Cc user v tn hiu chc nng ( Signal Function )Bn c th kt hp cc k hiu VTREG vi chc nng tm li ca Vision to

ra mt phng thc phc tp ca vic cung cp d liu ngoi c nhp vo ti ccchng trnh ca bn.

Chng trnh mu Measure s dng b gii m khi to file MEASURE.INI nh ngha cc tn hiu hm cho:

Xut hin xung rng ca trn ng vo A/D AD01. Xut hin sng sine trn ng vo A/D AD02. Xut hin tn hiu nhiu trn ng vo A/D AD03.

Tp tin MEASURE.INI c lu di dng Options for Target Debug Initialization File v c ni dung nh sau:/*-------------------------------------------*/

/* Function MyRegs() shows Registers R0...R3 */

/*-------------------------------------------*/

FUNC void MyRegs (void) {

printf ("---------- MyRegs() ----------\n");

printf (" R0 R1 R2 R3\n");

printf (" %02X %02X %02X %02X\n");

printf ("------------------------------\n");

}

//

// Generate Saw Tooth Signal on A/D input AD01

//


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signal void AD01_Saw (void) {

float volts; // peak-to-peak volatage

float frequency; // output frequency in Hz

float offset; // volatge offset

float duration; // duration in Seconds

float delay;

float val;

long i, end, steps;

volts = 2.0;

offset = 0.2;

frequency = 140;

duration = 8.0;

printf ("Saw Tooth Signal on A/D input AD01\n");

steps = 100;

delay = (0.01/frequency);

printf ("Saw Steps = %d\n", steps);

end = (duration * 10000);

for (i = 0 ; i < end; i++) {

val = (i % steps) / ((float) steps);

AD01 = (val * volts) + offset;

swatch (delay);

}

}

//

// Generate Sine Wave Signal on A/D input AD02

//

signal void AD02_Sine (void) {





float val;

long i, end;

volts = 1.4;

offset = 1.6;

frequency = 180;

duration = 5.0;

printf ("Sine Wave Signal on A/D input AD02\n");


for (i = 0 ; i < end; i++) {

val = __sin (frequency * (((float) STATES) / CLOCK) * 2 * 3.1415926);


swatch (0.0001); // in 100 uSec steps


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}

}

//

// Generate Noise Signal on A/D input AD03

//

signal void AD03_Noise (void) {





float val;

long i, end;

volts = 1.4;

offset = 1.6;

duration = 0.5;

printf ("Noise Signal on A/D input AD03\n");


for (i = 0 ; i < end; i++) {

val = ((float) rand (0)) / 32767.0;


swatch (0.00001); // in 10 uSec steps

}

}

//

// Run Signal Functions at Startup

//

signal void Startup (void) {

swatch (1.0); // wait 1.0 seconds

AD01_Saw ();


AD02_Sine ();


AD03_Noise ();

}

Startup (); // Start the Signals

define button "AD01 Saw Tooth", "AD01_Saw ()"

define button "AD02 Sine Wave", "AD02_Sine ()"

define button "AD03 Noise Signal", "AD03_Noise ()"


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Bn c th km theo chc nng d li cho nhng hm trong ca s OutputWindow Command Page.

>MyRegs ()

---------- MyRegs() ----------

R0 R1 R2 R3

00 00 00 00

Cho nhiu tn hiu chc nng ta c th dng hp cng c ToolBox cho cc yucu khn cp.

Thc hin phn tch (Performance Analyzer)Vision cho php bn thc hin vin phn tch tnh ton thi gian ca nhng ng

dng tch hp Performance Analyzer. chun b cho s phn tch tnh ton thi gian,ta dng vic thc thi chng trnh v mmenu Debug - Performance Analyzer mhp thoi Setup Performance Analyzer.

Bn c th chn cc k hiu hm hay nh tn hm hoc mt dy a ch khi dnghp thoi Setup Performance Analyzer .


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Thc hin cc bc thy vic thc hin phn tch:

mhp thoi Performance Analyzer

reset CPU v xa cc im ngt

nu chng trnh b dng khi bt u vic o c

mca sSerial Window#1 v g lnh S , g D.

Performance Analyzer cho ta thy biu dng ct trong mi phm vi.biu hnh ct cho thy phn trm thi gian thc hin on m trong mi phm vi. Click vomt ct thy thng tin thng k chi tit.

Phn tch tn hiu logicVi Logic Analyzer, Vision Debugger/Simulator cung cp mt mn hnh th

cho gi tr thay i ca bin hoc VTREGs.

Thc hin cc bc sau thy vic phn tch gi tr Logic hot ng:

Mhp thoi Logic Analyzer S dng hp thoi biu din cc tn hiu bn mun. Mt v d l AD01,

AD02, AD03 v mt cu trc nh l current.time.sec. Bn c th chngia nhiu kiu mu.

Chy chng trnh v hin th mc logic ng raLogic Analyzer cung cp mt mn hnh tnh ton thi gian chi tit ca cc tan

hiu chn.


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Sdng cc chip ngoi vi

y l cc thng s k thut m bn phi bit to nhng chng trnh dng ccchip ngoi vi v nhng t tnh ca h 8051. nhng thng sc cp trong chngny. Bn c th s dng cc on m c gii thiu c th nhanh chng lm vic vi8051.

y khng c cc chn t thit b ngoi vi trong 8051. thay vo chip8051 cung cp mt s s dng a dng cc chip ngoi vi phn bit gia chng vinhau. cc on m mu trong chng ny cho ta bit cch s dng cc h chip ngoi vic bit. Ch rng c nhiu ty chn cu hnh hn c gii thiu trong phn ny.

Start up code Special function Register Register bank Interrupt service Rountine Interrupt Enable Registors Parallel Port I/O Timer/counter Serial Interface Watchdog Timer D/A Coverter A/D Coverter Power Redution Modes


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M khi ng ( startup code )M khi ng c thc hin ngay lp tc khi ta reset ton b h thng v n thc

hin cc thao tc sau: Ph thuc vo s khc nhau ca thit b, nhng c tnh c bit ca thit

b. Xa ton b cc d liu (ty chn) Thit lp trng thi ban u gi tr cc ngn xp v con tr ngn xp(tychn) Thit lp trng thi ban u ca con tr ngn xp phn cng 8051 Chuyn i iu khin ti cc bin c thit lp hoc cc hm chnh ca

C.

Trnh bin dch Keil 51 cc thit bc bit c cc m khi ng khc nhau chtt. Mt m khi ng chung c cung cp trong tp tin ..\C51\LIB\STARTUP.A51.

Chc nng cc thanh ghi c bit (Special Function Registers)

Cc chip thit b ngoi vi ca 8051 c truy nhp s dng cc thanh ghi c chcnng c bit hoc SFRs. SRFs c nh v tr bn trong chip mt cch trc tip c a

ch t 80H n 0FFH. Nh pht trin Keil cung cp cc cng c gm cc tp tin hoccc file tiu c thnh ngha cc thanh ghi n cho bn. Bn c th s dng cc filetiu c cung cp sn hoc t to cho mnh mt file nh a ch cc chip ngoi vi.Ki bn to mt chng trnh vi Vision bn c th chn vic nh ngha cc thanh ghic bit ca thit b bng cch dng menu trong ca s lm vic.


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Nhiu chng trnh mu trong chng ny u s dng on m bt u nh sau:#include

Cc tp tin nh ngha thanh ghi c lu trong th mc C:\KEIL\C51\INC.on m sau y c trch t mt tp tin nh ngha thanh ghi cho cc port song songI/O .sfr P0 = 0x80; // 8-bit I/O Port P0

sfr P1 = 0x90; // 8-bit I/O Port P1

sfr P2 = 0xA0; // 8-bit I/O Port P2

sfr P3 = 0xB0; // 8-bit I/O Port P3

Bn c thnh cc gi tr SFRs mt cch trc tip bng cc m ngun C cc tiu flie.sfr IE = 0xA8; // Interrupt Enable register at SFR address 0xA8

sbit EA = IE^7; // global Interrupt Enable Flag (bit 7 of SFR IE)

Ch : Khi bn ly hoc ghi gi tr cc thanh ghi c bit bn cn phi khai bo

SFR trong tp tin ngun. Bit k hiu SFR ch c thnh ngha cho bit a ch ca thanh ghi SFR,

m n c nh v theo a ch 0x80, 0x88, 0x90 0xF8.Register Banks ( cc thanh ghi lu tr) Vi iu khin 8051 c xy dng da vo cc vng nhcn bn vi tm

thanh ghi thng dng (R0 R70). Mi thanh ghi l mt thanh ghi byte n.Tm thanh ghi a dng ny c th qun l vic lu tr v cc thanh ghi lutr.

8051 cung cp 4 thanh ghi lu tr m bn c th s dng. Qu trnh lmvic cbn ca cc thanh ghi d dng c nhn thy khi bn thc hinngt.

Dng cho chng trnh C trn 8051 th ta khng cn chn hoc mthanhghi v chng trnh mc inh chn thanh ghi lu tr 0. Cc thanh ghi lu tr 1, 2, 3 trong qu cc qu trnh ngt v trnh viclu tr v khi phc cc ngn xp.

Cc iu kin ngt ( Interrupt Service Routines )Trnh bin dch C51 cho php vit nhng iu kin ngt trong C. trnh bin dch

c s dng mt cch hiu qu bng m khi u v m kt thc v iu tit mccthanh ghi lu tr. Cc iu kin ngt c khai bo nh sau:void function_name (void) interrupt interrupt_number [using register_bank]

Ch s ngt (interrupt number) gip xc nh a ch vc tngt ca hm ngt. Sdng bng sau xc nh ch s ngt:

I n t e r r u p t N u m b e r A d d r e ss I n t e r r u p t N u m b e r A d d r e ss

0 (EXTERNAL INT 0) 0003h 16 0083h

1 (TIMER/COUNTER 0) 000Bh 17 008Bh

2 (EXTERNAL INT 1) 0013h 18 0093h

3 (TIMER/COUNTER 1) 001Bh 19 009Bh

4 (SERIAL PORT) 0023h 20 00A3h

5 (TIMER/COUNTER 2) 002Bh 21 00ABh

6 (PCA) 0033h 22 00B3h

7 003Bh 23 00BBh


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8 0043h 24 00C3h

9 004Bh 25 00CBh

10 0053h 26 00D3h

11 005Bh 27 00DBh

12 0063h 28 00E3h

13 006Bh 29 00EBh

14 0073h 30 00F3h

15 007Bh 31 00FBh

Vic s dng cc thuc tnh cho ta c th ch r mt thanh ghi lu tr trongsutt thi gian thc hin hm ngt. Nhng iu ngt khong ngn c th hiu qu hnkhng s dng thuc tnh, khi chng s dng thanh ghi lu tr 0. bn c th kim chng

bng hai on m essembler xem hiu qu ca chng.Ch :Cc hm km theo iu kin ngt cn phi c bin tp vi ch th NOAREGS.

Vic ny bo m rng vic bin dch khng pht sinh vic thay i cc thanh ghi tuyt

i. V d sau cho ta thy mt hm ngt tiu biu:#include // Special Function Registers of 80C51 CPU

#pragma NOAREGS // do not use absolute register symbols (ARx)

// for functions called from interrupt routines.

static void HandleTransmitInterrupt (void) {

:

:

}

static void HandleReceiveInterrupt (void) {

:

:}

#pragma AREGS // for other code it is save to use ARx symbols

static void com_isr (void) interrupt 4 using 1 {

if (TI) HandleTransmitInterrupt ();

if (RI) HandleReceiveInterrupt ();

}

Trong v d trn iu kin ngt chi ch s ngt 4 c thit lp. Tn ca hm ngtl com_isr. Khi lnh ngt c thc hin s ko theo, cc m mc c lu vo thanh ghiCPU v chn thanh ghi lu tr 1. Khi th tc ngt kt thc th gi tr cc thanh ghi ckhi phc.

Sau y l on m sinh ra bi lnh ngt k trn. Ch rng ni dung thanh ghilu tr sc hon i v c khi phc li sau khi thot.

; FUNCTION com_isr (BEGIN)

0000 C0E0 PUSH ACC ; Save the Accumulator and Data

Pointer

0002 C083 PUSH DPH

0004 C082 PUSH DPL

0006 C0D0 PUSH PSW ; Save PSW (and the current Register Bank)

0008 75D008 MOV PSW,#08H ; This selects Register Bank 1


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:

:

0052 D0D0 POP PSW ; Restore PSW (and prior reg bank)

0054 D082 POP DPL

0056 D083 POP DPH

0058 D0E0 POP ACC ; Restore the Accumulatorand DPTR

005A 32 RETI

; FUNCTION com_isr (END)

Cc thanh ghi cho php ngt (Interrupt Enable Registers)8051 cung cp iu kin ngt cho nhiu chip ngoi vi. Qu trnh ngt hon ton

ph thuc vo bit EA ca Interrupt Enable (IE) SFR. Khi bit EA ln mc 1 th qu trnhngt c thc hin. Khi bit EA xung mc 0 th qu trnh ngt b v hiu.

Mi qu trnh ngt th c kim sot bi than ghi IE SFR. Tn mt s chip 8051c th c hn 1 thanh ghi IE. Kim tra ti liu v chip tn dng cc qu trnh ngt.

Cc port song song vo/ra (Parallel Port I/O)Mt chip 8051 bnh thng c 4 port vo ra song song m bn c th kt ni vi

cc thit b ngoi vi. Chng l Port 0, Port 1, Port 2, Port 3. Mt s IC 8051 mrng cti 8 Port xut nhp.

Por t D i rect ion Wid th A l t e rna te use

P0 I/O 8 bits Mux'd. 8-bit bus: A0-A7 & D0-D7

P1 I/O 8 bits P1.0-P1.7: Available for user I/O

P2 I/O 8 bits Mux'd. 8-bit bus: A8-A15

P3 I/O 8 bits P3.0: RXD (Serial Port Receive)

P3.1: TXD (Serial Port Transmit)

P3.2: /INT0 (Interrupt 0 input)

P3.3: /INT1 (Interrupt 1 input)

P3.4: T0 (Timer/Counter 0 Input)

P3.5: T1 (Timer/Counter 1 Input)

P3.6: /WR (Write Data Control)

P3.7: /RD (Read Data Control)

Cc Port trn IC 8051 bnh thng th khng c cc d liu trn thanh ghi iukhin. Thay vo , cc chn ca Port 1, Port 2, Port 3 mi chn c th tng ln mchng c th l u nhp hay u xut. ghi gi tr vo mt Port bn chn gin ghigi tr tng chn ca Port . ly gi tr t Port trc ht gi tr ca chn phi c

ghi l 1 ( y cng l gi tr ban u sau khi RESET ).V d sau l chng trnh ghi v xut gi tr cc Port I/O:sfr P1 = 0x90; // SFR definition for Port 1

sfr P3 = 0xB0; // SFR definition for Port 3

sbit DIPswitch = P1^4; // DIP switch input on Port 1 bit 4

sbit greenLED = P1^5; // green LED output on Port 1 bit 5

void main (void) {

unsigned char inval;


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inval = 0; // initial value for inval

while (1) {

if (DIPswitch == 1) { // check if input P1.4 is high

inval = P1 & 0x0F; // read bit 0 .. 3 from P1

greenLED = 0; // set output P1.5 to low

}

else { // if input P1.4 is low

greenLED = 1; // set output P1.5 to high

}

P3 = (P3 & 0xF0) | inval; // output inval to P3.0 .. P3.3

}

}

Timer/Counter ( bnh thi v bm )IC 80C52 c ba b Timer/Counter (Timer 0, Timer 1, v Timer 2). Timer 1 v

Timer 0 c cc chc nng thng thng nh nhau trong khi Timer 2 c kh nng ngdng cao hn. Cc timer c th hot ng c lp vi nhau vi cc kiu nh thi, kiu

m, kiu pht tc baud (cho cc Port tun t).Chng trnh sau l mt v d dng Timer 1 to mt xung vung c tn s 10KHz.#include

/*

* Timer 1 Interrupt Service Routine: executes every 100 clock cycles

*/

static unsigned long overflow_count = 0;

void timer1_ISR (void) interrupt 3 {

overflow_count++; // Increment the overflow count

}

/*

* MAIN C function: sets Timer1 for 8-bit timer w/reload (mode 2).

* The timer counts to 255, overflows, is reloaded with 156, and

* generates an interrupt.

*/

void main (void) {

TMOD = (TMOD & 0x0F) | 0x20; // Set Mode (8-bit timer with

reload)

TH1 = 256 - 100; // Reload TL1 to count 100 clocks

TL1 = TH1;

ET1 = 1; // Enable Timer 1 Interrupts

TR1 = 1; // Start Timer 1 Running

EA = 1; // Global Interrupt Enable

while (1); // Do Nothing (endless-loop): the

timer 1 ISR will


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// occur every 100 clocks. Since the

80C51 CPU runs

// at 12 MHz, the interrupt happens

10 KHz.

}

B bin i tng t sCc b bin i tng t s A/D l cc linh kin ch c trn mt s thnh vin ca

h 8051 nhng kh ph bin. Cc b bin i A/D thng c iu khin thng quathanh ghi ch ADCON, thanh ghi ny c gn cho mt v tr cn trng no trongon nhdnh cho cc SFR, thanh chi ADCON cho php ngi s dng chn la knhcn c bin i A/D, bu mt bin i mi v kim tra trng thi ca ln bin ihin ti.

Cc b bin i A/D in hnh cn 40 chu k lnh hoc t hn hon tt vicbin i v chng c cu hnh to ra ngt vo lc hon tt vic bin i, vic nylm cho b vi iu khin nh hng n mt vector ngt c th dnh cho vic bin iA/D. thng thng khuyt im ca b bin i A/D l b ny yu cu b vi iu khin

phi mc tnh cc thay v i vo ngh chngt do vic bin i hon tt. Kt quca vic bin i c c t mt SFR khc hoc mt cp SFR, ph thuc vo phngii ca b bin i.

Chng trnh sau l v d chuyn i tng t t tn hiu ng vo sang s:#include

#include

void main (void) {

unsigned char chan_2_convert;

SCON = 0x50; // Configure the serial port.

TMOD |= 0x20;

TH1 = 0xA0;TR1 = 1;

TI = 1;

// Configure A/D to sequentially convert each input

channel.

ADCCON1 = 0x7C; // 0111 1100

while (1) {

unsigned int conv_val;

unsigned char channel;

// Start a conversion and wait for it to complete.

chan_2_convert = (chan_2_convert + 1) % 8;

ADCCON2 = (ADCCON2 & 0xF0) | chan_2_convert;

SCONV = 1;

while (ADCCON3 & 0x80);

// Read A/D data and print it out.

channel = ADCDATAH >> 4;


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conv_val = ADCDATAL | ((ADCDATAH & 0x0F)


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iu khin cp in (Power Reduction Modes)Ch ngh (Idle mode) c kch hot bng cch thit lp bit IDLE bng 1. ch

ngh lm dng mi vic thc thi chng trnh. Cc ni dung trn RAM c bo tonv mch dao ng tip tc hot ng nhng xung clock b kh khng n c CPU.Cc bnh thi v UART tip tc thc hin bn thng cc chc nng ca chng.

Ch nghc kt thc bng cch kch hot mt im ngt bt k. Khi vic

thc thile65nh ngt ISR kt thc th h thng s lm vic li t lnh set bit IDLE ln 1.Sau y l chng trnh thc hin ch ngh:sfr PCON = 0x87;

void main (void) {

while (1) {

task_a ();

task_b ();

task_c ();

PCON |= 0x01; /* Enter IDLE Mode - Wait for enabled interrupt */

}

}

Ch gim cp in ( power down mode) c thit lp bng cch set bitPDWN ln 1. trong ch nyma5ch dao ng trong chip b dng. Nh vy cc bnhthi v UART cng nh vic thc hin phn mm u tm ngng. Min l c in p tithiu 2V t vo chip th cc ni dung lu trn RAM vn c bo ton.

Cch duy nht buc b vi iu khin ra khi ch gim cng sut l p tthit lp li (RESET) b vi iu khin ny khi cp in.

Sau y l chng trnh th hin qu trnh gim cp in:sfr PCON = 0x87;

void main (void) {while (1) {

task_a ();

task_b ();

task_c ();

PCON |= 0x02; /* Enter Power Down Mode */

}

}

Bnh thi WATCHDOGBnh thi Watchdog c sn trn nhm mrng ca cc thnh vin h 8051.

mc ch ca bnh thi Watchdog l thit lp li (reset) li b vi iu khin nu bnh thi khng c cung cp mt trnh t thao tc c th trong mt khong thi gianxc nh. iu ny ngn nga vic np li Wachdog mt cch trng khp ngu nhin bicc phn mm khc.

Trong h 8051, watchdog thng c thc hin di dng mt bnh thi khctrn chip, bnh thi ny lp t l gim tn s mch dao ng h thng v kn mxung clock c chia t l. Khi bnh thi quay vng, h thng thit lp li tu(reset). Watchdog c thc cu hnh i vi tc quay vng v thng c thcs dng lm bnh thi khc mc d y l bnh thi c phn gii thp.


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n Tt Nghip


Chng trnh sau y cho thy cch thit lp gi tr ban u v reset watchdog:

#include

/* This function adjusts the watchdog timer compare value to the current

* PCA timer value + 0xFF00. Note that you must write to CCAP4L first,

* then write to CCAP4H. */

void watchdog_reset (void) {

unsigned char newval;

newval = CH + 0xFF;

CCAP4L = 0;

CCAP4H = newval;

}

void main (void) {

unsigned int i;

/* Configure PCA Module 4 as the watchdog and make

sure it doesn't time-out immediately. */

watchdog_reset ();

CCAPM4 = 0x48;

/* Configure the PCA for watchdog timer. */

CMOD = (CMOD & 0x01) | 0x40;

/* Start the PCA Timer: From this point on, we must reset the watchdog

timer every 0xFF00 clock cycles. If we don't, the watchdog timer

will reset the MCU. */

CR = 1;

/* Do something for a while and make sure that we don't get reset by

the watchdog. */

for (i = 0; i < 1000; i++) {

watchdog_reset ();

}

/* Stop updating the watchdog and we should get reset. */

while (1);

}


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n Tt Nghip


PHN III

THI CNG MCH VNG DNG LP TRNH C TRONG AT89C2051

I.iu khin led nS nguyn l:

Code C:#include < at892051.h >

char constnum[ ] = {0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 };voidwait (void)

{ ;}

voidmain(void)

{unsigned int i;

unsigned char j;P1 = 0;

while(1){

for( j = 0; j < 8; j++ ){

P1 = num[ j ];

for( i = 0; i < 10000; i++ ){

wait();

}

}}

}


61/66

n Tt Nghi

II. NGS

Code#include

charnu voidw

{ ; }

voidma unsig

unsig

P1 =P3 =

for( ;;

for({

P3fo

}

}

}

p

DNG C nguyn

C:at892051

[ ] = {0x3it (void)

in (void){ned charc

ned inti;

0;0;

){ight=0;rig

= right;(cnt=0;c

P1 = numfor(i = 0;{

wait();}

}

HO 2 Ll:

.h >

,0x06,0x5

t, right;

ht


62/66

I

n Tt Nghi

II.NG S

Code#include

char c

voidwai

{ ;

}

voidmai

{

unsig

unsig

P3 =

P1 =

for( ;;

{

colfor

{

fo

p

NG CNguyn

C:< at892051.

onstpat[5]

t (void)

n(void)

ed charcn

ed inti;

0;

0;

)

1;(cnt=0;cnt

{ 0x3f, 0x0

, col;

5;cnt++)

l < 32;col

do an lap trinh c cho ho vi dieu khien 8051

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