development of a modern airbag system prototype · airbag soc asic m ain µ c satellite sensors...
TRANSCRIPT
Development of a modern Airbag System Prototype COSIDE User Experience
Dr. Thang Nguyen (Infineon Technologies Austria AG)
SystemC AMS – COSIDE® User Group Meeting 2014
Agenda
1. Overview of Airbag System Application
2. Motivations
3. FPGA-based Development Framework
4. Accelerated System Co-Verification Framework
5. COSIDE Use Cases by IFAT
6. Real-life case study
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Airbag System Application – Overview & Challenges
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Airbag SoCASIC
Main µC
Satellite Sensors (upfront & side impact, g-sensor,
buckle switches...)
Airbag ECU
Actuators (Squibs)
Airbag System Overview(Sensors <--> Controller <--> Actuators)
SP
I_IFa
na
log
ue
an
alo
gu
e
Embedded
SW
Target System-under-Evaluation • Sophisticated = Safety Critical Real-
time Embedded (SW/FW) Mixed-Signal
• Cost-Reduction = high integration
challenges in verification effort
ModuleReg_IF
ModuleDigital Logic
Sub-System Digital (RTL)
A/D
_IF
Digital CORE
SPIHW
FW
Digital Toplevel
CENTRAL_Dig (RTL)
(RTL)
SoC Power SupplyModels SoC_PWR
Safing_Engine (SE)
SE - Digital CORE
SPIHW
SE_AFEModel(VHDL)
(RTL)
A/D
_IF
SMPS Modules(Buck/Boost
Converter)(VHDL)
iPSG(VHDL)
CENTRAL_AFE(Diagnostic and
Monitoring)Model(VHDL)
LVRs(VHDL)
Supply_net
rese
t
Sup
ply
_ne
t
Sup
ply
_ne
t
Airbag SoC Chipset TL Architecture
sys_
clk
iLVRs(VHDL)
Modules AFE
Sensor_IF(PSI or DSI)
SQB_Driver x Loops HS&LS
Vo
lta
ge
Me
asu
rem
en
t
Watchdog
GPA-IO
PWR_Train IF (CAN/LIN)
Main
µCSPI_IF
On-Board Sensors
SMPS_Dig and LVRs_Dig (RTL)
Motivations
4
Interactive Concept Development
Support test scenario where SIM is impractical
Early (before Integration&Test)
Concept Verification
System Validation
Late bugs are expensive!!
2014-01-0240
Rapid Prototyping (Emulation) can help!
FPGA-based Development Workflow
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Ref: Nguyen.T (IFAT) et. Wooters.S (TRW), SAE 2014 "FPGA-Based Development for Sophisticated Automotive Embedded Safety Critical System"
Advantages of FPGA-based SoC Emulation System
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Accelerated System Co-Verification Framework
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Design Sign-Off
HIL basedTester
DU
T
Imple
menta
tions
DUTMixed
Abstraction
DUTSystemC
(behavioral)
DUT-FPGA Prototype
DUT-ASIC Silicon
Simulation based Environment
UVM-SystemC Environment
re-use
MonitorDriver
UVM-SystemCEnvironment
MonitorDriver
Lab ValidationVerification
Test
Environm
ent
Abstraction level
Highlights:
Acceleration of verification activity, including scenarios which are impractical for simulation
Reuse Link between Pre-SI and Lab Evaluation
Cost-effective HIL-based tester, e.g.: Zedboard vs. dSPACE
UVM Layering concept
Ref: Nguyen.T (IFAT) et. P.Erhlich, T.Vörtler (FhG), DVCON Europe 2014 "UVM-SystemC based HIL-Simulations for accelerated System Co-Verification"
Use Cases by IFAT
1. FPGA Toplevel Integration and Front-End Design
especially, Analog Functional Stub Modeling
2. Supporting FPGA Back-End Implementation
a) Scripting for Xilinx ISE for System HW realization
b) Data2Mem scripting for System Firmware update
3. Verification & Lab Validation of the Prototype
a) Test Scenarios Development
b) Test Stimulus Development and Validation
c) Test Bench Generation and Test execution (@ SIM & physical HW)
d) SIM root-cause analysis and bug-fix testing support
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Case study: Real-life Airbag SoC Sensor IF
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DSI3 Sensor Emulyzer/RealDSI3 Sensor
Emulyzer/RealDSI3 Sensor Emulyzer/Real
FPGA_SoC_TOP
Main µC/SPI
Emulator
Airbag_Dig
Sensor TxR logic
(DUT1)SP
I H
W I
F
Ext
_Dat
aX_
IF
TC_Board
AFE Analogue TC
(DUT2)
Ext
_Dat
aX_
IF
DSI/PSI Sensor Emulyzer/Real
init_sync
Trans_ctrl
12
/2
4/
36
Mh
Z
Vdsi_X
(X=1..6)
SPI_IF
FPGA Mother BoardWorkstation with StubFnc Ctrl Software
RS232/RJ-45
Airbag_AFEStubFunC
· Testing/evaluating the new implementation of sensor TxR
· Paremetric testing of AFE circuit implementation
HIL_Tester, e.g.: Zedboard with the
reuse of UVM-SystemC TB
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