developing with the arm cortex-m3 processor to …rtcgroup.com/arm/2007/presentations/115 -...

1Confidential

Developing with the ARMCortex-M3 Processor to Bridge8-bit and Next Generation High-Performance Microcontrollers

Shyam Sadasivan

2Confidential

Cortex-M3 – Bridging To The Future

Introduction

Ideal bridge from 8/16 bit architectures

The need for migration

Easy to program

Hard real-time application support

Meeting needs of next generation microcontrollers

Ultra low-power implementation

Advanced application security via memory protection

Enhanced visibility with advanced debug and trace

Summary

3Confidential

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http://www.lpmm-book.org

4Confidential

32-Bit growth eclipsing 16-Bit and 8-Bit stagnating

Requirement for standard processor to enable code reuse

Vendor differentiation through custom peripherals

Speed-to-market is the key to obtaining a competitive edge

Gartner

0%

5%

10%

15%

20%

25%

30%

8-Bit 16-Bit 32-Bit

MCU Unit Growth 2005/2004

Gartner

0.3%

9.7%

27.8%

LEGO Mindstorm NXT

$M$M

Gartner

MCU Revenue

Estimated

MCU Market Is Adopting 32-Bit Fast

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Application Complexity

Why 32-bit CPUs For Microcontrollers ?

Improving Code Reuse

IR FireDetector

IntelligentVendingTele-parking

Energy EfficientAppliances

UtilityMetersIntelligent Toys

ExerciseMachines

Device Aggregation

Increasing System Connectivity

Reduced Development Barriers

Accelerating Time To Market

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The Cortex-M3 Processor ARM v7M architecture

Tightly integrated core

Advanced inbuilt custom system peripherals

CM3Core Central Core

High efficiency 1.25 DMIPS/MHz

Harvard bus architecture

3-stage pipeline with branch speculation

Thumb®-2 and traditional Thumb only

Hardware divide and single cycle multiply

Cortex-M3 Processor integrates CM3Core with

Configurable NVIC

Advanced debug components

Optional MPU and Embedded Trace Macrocell™

Code/SRAM interfaces

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Cortex-M3 Designed For The Future Low Power

Low dynamic power

Fully synthesisable

System level power reduction

uA device standby

Advanced Application Security

Code isolation being demanded

Security requirements crossing domains

Optional Memory Protection Unit

Debug & Trace

Low-cost system visualization key

Code Instrumentation

Single Pin Trace

Reduced Pin Debug

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Introduction



Easy to program






Summary

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Options For 8/16 Bit Users Today

Option #2

Migrate to an efficient 32-bit processorrunning at a lower frequency

Option #1

Load 8/16 bit

devices more

than they are

designed for

To meet

performance

requirements

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8051 In The Modern World

Limited support for modern techniques

Little code reuse, difficult to move code between 8051 devices

Lack of good RTOS support

C programming new to 8051

Assembly language skills not common today

Legacy application code

Difficult to maintain

Very hard to port new 8051 devices

Easier to move to new modern architecture like the Cortex-M3

8051 offers few debugging options

Monitor programs like Keil MON51 are required

JTAG debugging is available on few devices

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Cortex-M3 Bridge To Next Generation

System visibility

Real-time functionality

Good interrupt response

Atomic bit manipulation

Traditional Features

Little RTOS support

Fragmented devices

Code density

Limited performance

Memory restrictions

Assembly required

Challenges

8/16 bit Cortex-M3

x

Leading RTOS support

Code portability

Thumb2 code density

1.25 DMIPS/MHz

4GB addressable space

Native C target

Solutions

Familiarity in 32-bit

xxxxx

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Introduction



Easy to program






Summary

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Which Is Better ?

Stop

Please bring your vehicle to aspeed not exceeding zeromiles per hour at thiscoordinate in space and timeas there is other vehiculartraffic moving in a directionperpendicular to your ownand may intersect with yourvehicle’s current trajectory.

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Cortex-M3 Easy To Program

Vector Table Interrupt entry/exit stubs

Optimized compile

Initialization codeException Handler

Unaligned data access

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ENTRY

LDR PC, Reset_Addr

LDR PC, Undefined_Addr

LDR PC, SWI_Addr

LDR PC, Prefetch_Addr

LDR PC, Abort_Addr

NOP ; Reserved vector

LDR PC, IRQ_Addr

LDR PC, FIQ_Addr

IMPORT Reset_Handler ; In init.s

IMPORT inc_clock [WEAK] ; In clock_irq.c

Reset_Addr DCD Reset_Handler

Undefined_Addr DCD Undefined_Handler

SWI_Addr DCD SWI_Handler

Prefetch_Addr DCD Prefetch_Handler

Abort_Addr DCD Abort_Handler

IRQ_Addr DCD IRQ_Handler

FIQ_Addr DCD FIQ_Handler

ISR_VECTOR_TABLE vector_table_at_0 {

stack_base + sizeof(stack_base),

ResetISR,

NmiSR,

FaultISR,

0, // Populate if using MemManage (MPU)

0, // Populate if using Bus fault

0, // Populate if using Usage Fault

0, 0, 0, 0, // reserved slots

SVCallISR,

0, // Populate if using a debug monitor

0, // Reserved

0, // Populate if using pendable service request

0, // Populate if using SysTick

// external interrupts start here

Timer1ISR,

GpioInISR

GpioOutISR,

I2CIsr

};

ARM7 Cortex-M3

Cortex-M3 Vector Table In Just C

No Assembly, Just C

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Cortex-M3 Function Handler In Just C Register stacking in hardware

Fast and deterministic

12 Cycles into interrupt

6 Cycles tail chaining

No assembler required

For start-up

For reset

For NMI

For fault handler

For interrupt entry & exit

No interworking required

No Thumb-ARM transition

Exceptions traditionally handledin ARM mode

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Cortex-M3 Bit Banding

Purely software drivenSplittable by interrupt

LDR R0,=0x200FFFFF ; Setup address

MOV R2, #0x4 ; Setup data

LDR R1, [R0] ; Read

ORR R1, R2 ; Modify bit

STR R1, [R0] ; Write back result

LDR R0,=0x23FFFFFC ; Setup address

MOV R1, #0x1 ; Setup data

STR R1, [R0] ; Write

Traditional bit manipulation Cortex-M3 bit banding

Efficient hardware executionAtomic !

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Introduction



Easy to program






Summary

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Push ISR 1 Pop PopISR 2Push

26 Cycles 26 Cycles16 Cycles 16 Cycles

Interrupt Response – Tail ChainingHighest

IRQ1

IRQ2

ARM7TDMI

Interrupt Handling

Cortex-M3Interrupt Handling

ISR 1 PopISR 2

6 Cycles 12 Cycles

Push

12 Cycles

Tail-Chaining

65% SavingCycle Overhead

26 cycles from IRQ1 to ISR1

(up to 42 cycles if in LSM)

42 cycles from ISR1 exit to ISR2 entry

16 cycles to return from ISR2

ARM7TDMI

12 cycles from IRQ1 to ISR1

(Interruptible/Continual LSM)

6 cycles from ISR1 exit to ISR2 entry

12 cycles to return from ISR2

Cortex-M3

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Deterministic Interrupt ResponseHighest

priority

IRQ1

IRQ2

ISR 2Starts

PopISR 3Push

NMI

IRQ3

NMI ISR 1 ISR 2Push

Push for ISR1 begins

Following NMI tail-chaining commences

Pop only occurs on return to “Main”Pre-empted by NMI

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Cortex-M3 RTOS Support

Cortex-M3 has many RTOS-friendly features

SYSTICK

Countdown timer, OS heartbeat

NVIC

Standardized interrupt service

PendSV

Faster/easier context switch

NicheTask™

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Introduction



Easy to program






Summary

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How Low Is Ultra Low ?

½

3-6

1-3

Animal Tracking

Pacemakers

Tim

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etw

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nre

cha

rge

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2-3

5+ years

ZigBee

Ultra-Low Power

Bluetooth

Po

we

rC

onsum

ptio

n

hour

hours

days

years

W

W

mW

mW

µW

Near Field

Communication

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Cortex-M3 Power Consumption at 1MHz

0

2

4

6

8

10

Po

we

r(m

W)

Standby

1µW

Sleep

10 µW

Active

0.3 mW

All numbers for minimal config of Cortex-M3 processor on TSMC 0.18G, ARM Metro library, measured under typical conditions – 1.8V, 25C, typical silicon

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Cortex-M3 Sleep Mode Signals/Triggers

WFI or WFE

Sleep Mode

Active Mode

SLEEPONEXIT bit set

Sleep Mode

System Level Sleep Possible

Active Mode

Sleep Now

Sleep On Exit

Deep Sleep

Immediate sleep mode entry

Sleep entry on ISR completion

Communicate to system

that deeper sleep is possible

ISRActive Mode

SLEEPDEEP bit set

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Cortex-M3 Sleep Mode Example

HCLK OFF

FCLK reduced (1 MHz)

Sleep

Active

HCLK high speed (32 MHz)

FCLK high speed (32 MHz)

HCLK OFF

FCLK reduced (32 KHz)

Deep sleep

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µDMA Controller For Lower Power

PL230

µDMA

Cortex-M3

AHB Bus Matrix

APB

Flash SRAM

Peripheral

DMA Done

Peripheral

DMAREQ/ACK

Peripheral

Peripheral

Simple to include in system

1x APB (v3) port

1x AMBA® AHB™-Lite port

Plus direct access to on-chip memory

Simple programmer’s model

Moveable position in memory map

All registers defined as base + offset

Configurable

1-32 independent channels

2 levels of priority

Optimized for use with Cortex-M3

Tightly integrated with NVIC

3-10 kgates

Memory-to-MemoryMemory-to-PeripheralPeripheral-to-Memory

Supports

Interface

28Confidential

µDMA – Efficient Data Transfer

0 1 2 3 4 5 6

R: CtrlWord Data CtrlWord

R: SrcAddr Data SrcAddr

R: DestAddr Data DestAddr

R: *SrcAddr Data *SrcAddr

W: *DestAddr Data *DestAddr

W: CtrlWord Data CtrlWord

xxx

Notes:

R: - AHB address phase for read

W: - AHB address phase for write

Data – AHB Data phase

*Addr = address from location Addr

μDMA Controller – 6 cycles to copy a word

Cortex-M3 processor interrupt routine – 34 cycles

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

12 cycles// copy one word

{--count; *ptr_to++ = *ptr_from++;

If (count <= 0)

{ // signal that block is finished} }

12 cycles10 cycles

29Confidential


Introduction



Easy to program






Summary

30Confidential

Aggregation of multiple devices

Single processor, multiple applications from different vendors

Many individual tasks having different memory requirements

Why Application Security Is Necessary

Example : Automotive Systems

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MPU enables

Separation of processes

Enforcement of privilege rules

Enforcement of access rules

MPU provides full support for

Protection regions

Overlapping protection regions

Access Permissions

Exporting memory attributes to the system

Up to 8 regions each split in to 8 sub-regions

32 Byte to 4GB regions

Cortex-M3 Memory Protection Unit

32Confidential

How Cortex-M3 Memory Protection Works

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Attribute And Size Register

0xE000EDA0

AP: Data access permission field

Read-onlyRead-onlyb111

Read-onlyRead-onlyb110

No accessRead-onlyb101

ReservedReservedb100

Read/WriteRead/Writeb011

Read-onlyRead/Writeb010

No accessRead/Writeb001

No accessNo accessb000

Userpermissions

Privilegedpermissions

Value

Size: MPU Protection Region Size

16KBb01101

4GBb11111

2GBb11110

……

32KBb01110

……

128Bb00110

64Bb00101

32Bb00100

SizeRegion

XN: Instruction access disable bit

TEX: Type extension field

S: Sharable bit

C: Cacheable bit

B: Buffearable bit

SRD: Sub-Region Disable

example: b00001111

disables top half of region

ENA: Region enable bit

Controls the MPU access permissions

34Confidential

Simple MPU Setup

Regions are configured via a pair of registers

Base Address Register

Attribute and Size Register

Alias registers duplicate the register pair

Up to 4 regions can be configured with an STM instruction

; R1 = 4 region pairs from process control block (8 words)MOV R0, #NVIC_BASEADD R0, #MPU_REG_CTRLLDM R1, [R2-R9] ; load region information for 4 regionsSTM R0, [R2-R9] ; update all 4 regions at once

35Confidential


Introduction



Easy to program






Summary

36Confidential

Why advanced debug and trace ?

Easier debugging for faster development

Improved system visibility - all registers visible

Active interrupt, Interrupt Pending visible

Non-intrusive debug and trace for real-time

Allow interrupts to be taken during debug

Instrumentation trace enables profiling

Low cost paramount !

Low pin count for lower packaging costs

Cortex-M3 - 2 pins for SWD debug, 1 pin for SWV trace

37Confidential

Cortex-M3 Hardware Debug

In-circuit emulation control

Free run, halt and single step

Non-intrusive detection of lock up, reset, sleeping, or in a wait-state

Breakpoints

FPB supports six instruction breakpoint words

Watchpoints

Contains 4 watchpoint comparators

Memory access

Non-intrusive memory read/write while target is running

Debug interface

Serial-wire debug-port (SW-DP)

Combined JTAG and serial-wire debug-port (SWJ-DP)

38Confidential

Variety Of Cortex-M3 Trace OptionsData Watchpoint and Trace Unit

Data Trace

Instruction Trace Macrocell

Printf style debugging

Trace Port Interface Unit

Option #1- ITM Only

TPIU

DWTCM3Core

ITM

ETM

SWV

S/W Trace

Instr Trace TriggerETM port

Embedded Trace Macrocell

Instruction trace only

Watch continously

Complex triggering

Filtering

Option #2 - ITM + ETM Trace

Data

Trace

39Confidential

Full Trace Solution For Cortex-M3

AHB Trace Macrocell (HTM)

Address and data trace information from the buses

Event recognition to generate trigger events

Generates trace data output through AMBA Trace Bus

Completely non-intrusive

HTM HTMPort

TPIU

DWTCM3Core

ITM

ETM

SWV

ETMPort

AHB Bus

40Confidential


Introduction



Easy to program






Summary

41Confidential

Cortex-M3 - Best Of Both Worlds

Leading RTOS support

Code portability

Thumb2 code density

1.25 DMIPS/MHz

4GB addressable space

Native C target

Best of 32-bit

Atomic bit manipulation

Good interrupt response

Real-time functionality

System visibility

Best of 8/16-bit

42Confidential

Thank you

http://www.lpmm-book.org

developing with the arm cortex-m3 processor to …rtcgroup.com/arm/2007/presentations/115 -...

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