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ARM Cortex board

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ARM Cortex STM series

STM32 Series

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Abbreviation • FS full speed

• HS high speed

• MC motor controller

• MSI multi speed internal oscillator

• RNG random number generator

• SDIO secure digital input output

• VScal voltage scaling

• DSC digital signal controller

• PGA programmable gain ampilier 4

STM32F4xx block diagram

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Memory map (1)

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Memory Map (2)

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Memory Map (3)

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ARM Bus

• Introduced by ARM Ltd in 1996

• Widely used as the on-chip bus

ARM BUS

• AMBA = ARM Memory Bus Architecture

• AHB = ARM High performance Bus

• APB = ARM Peripheral Bus

• AMBA-AHB connects ARM core with

memory, external DRAM

• AMBA-APB interfaces ARM core with

external low-speed I/O devices using

AMBA-APB bridge

AMBA

• AMBA-AHB connects to 32-bit data and

32-bit address at high speed

• AHB maximum bps bandwidth is 16 times

ARM processor clock

• AMBA-APB bridge is used to

communicate AHB bus to APB bus

• The bridge communicates to memory

through AMBA-AHB

AHB Bus

• AHB Bus are interconnected with:

– Cortex core

– Internal SRAM

– Internal Flash memory

– FSMC (Flexible Static Memory Controller)

– AHB to APB

– DMA

– Ethernet DMA

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APB bus

Connect:

• I2C

• Touch screen

• SDIO

• MMC (multimedia-bus)

• USB

• CAN bus

ARM BUS

System architecture

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System architecture connecting devices

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Bus system

• Icode bus : connects the instruction bus to the flash

memory instruction interface (FLITF)

• Dcode bus : connects to flash memory data interface

and debug access

• System bus : connects to bus matrix that manages the

arbitration between core and DMA

• DMA bus: AHB master interface of the DMA to bus

matrix

• Bus matrix: arbitrations between different buses

• AHB/APB bridge: bridge between AHB and APB

APB1 is limited at 45 MHz and APB2 is at 90 MHz

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AHB and APB

• AHB = Advance High Performance Bus with

max speed = 180 Mhz

• APB = Advance Peripheral Bus with APB1 max

speed = 45 Mhz and APB2 max speed = 90

MHz

• FSMC = Flexible static memory controller (able

to interface with synchronous and

asynchronous)

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Cyclic redundancy checking (CRC)

• Use to get a CRC code from a 32 bit data word

• Use to verify data transmission and storage

integrity

• Example of CRC calculation block diagram

• Example of CRC polynomial:

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Power supply overview

• The device requires 1.2-3.3V voltage supply.

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Power supply

• Voltage regulator to provide 1.2V for core

and memory

• Reset and Clock control, real time clock,

and LSE (Low speed external crystal)

oscillator are supported by backup domain

power source

• BDCR = Backup Domain Control Register 21

Low power mode

• Normal condition: run mode

• Low power mode:

– Sleep mode

CPU clocks are off, all peripherals are running

– Stop mode

all clocks are off

– Standby mode

1.2 V power domain is off (enter backup domain)

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Low power mode

WFI (wait for interrupt) and WFE (wait for event) are special ARM

instructions

PDDS = Power down deep sleep. LPDS = Low-Power Deep sleep

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Reset

There are 3 types of reset:

• System reset

• Power reset

• Backup domain reset

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System reset

Set all registers to their reset values except reset

flags and registers in the backup domain

It is generated when:

• External reset pin is triggered

• Window watchdog ends of count condition

(WWDG reset)

• Independent watchdog ends of count condition

(IWDG reset)

• Software reset (SW reset)

• Low power management reset

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Power reset

Set all registers to their reset values except

registers in the backup domain

It is generated when:

• Power on/ Power down reset

• When exiting standby mode

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Backup domain reset

Effects only the backup domain

It is generated when:

• Software reset

• VDD or VBAT, if both supplies have previously

been off

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STM32F4xxx board

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STM32F4 Hardware diagram

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STM32F4 Hardware diagram

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Clocks Three different clock sources can be used to drive

SYSCLK

• HSI (High speed Internal) oscillator clock

• HSE (High speed External) oscillator clock

• PLL clock

The devices have two secondary clock sources

• 32 kHz low speed internal (LSI) RC for the

independent watchdog and optionally drive RTC

• 32.768 kHz low speed external crystal (LSE) which

optionally drive RTC

Each clock source can be switched on/off independently 31

CLOCK

• HSI clock: provides a clock source at low

cost (no external component)

• HSE clock: provides higher accuracy

• LSE clock: low power, but high accuracy

• LSI clock: low power for stop and standby

mode

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SYSCLOCK

• After a system reset, HSI is selected as

system clock

• A switch from one clock source to another

occurs only if target clock source is ready

• If a target is not yet ready, the switch will

occur after the target is ready

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Clock Tree

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Clock Tree

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Our board

• HSE is 4-26 MHz crystal (16 MHz our case)

• HSI is 16 MHz

• PLL = Up to 168 MHz (Max. freq.)

• SYSCLK can be selected from PLL, HSE,

or HSI 36

Real Time Clock (RTC)

• RTC can be either HSE (1MHz), LSE or

LSI clock which is set by the backup

domain control register

• If LSE is selected, RTC continues to work

even if system or backup supplies

disapeear

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Watchdog and clockout

• If independent watchdog is started either

by hardware or software, LSI oscillator is

forced ON and will supply the watchdog

• Microcontroller clock output (MCO pin)

allows clock to be outputted by selected

from: SYSCLOCK, HSI, HSE, PLL

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Output clock

• HCLK : for AHB bus, core, memory and DMA

• FCLK: free running clock

• APBx

• APBxTIMCLK

• ADCCLK: to ADC module

• I2S Clock

• Ethernet clock

• USB clock 39

Reset and Clock Control (RCC)

• RCC is a set of register to setup for reset

and clock control

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Internet/External clock setup

This section provide functions allowing to configure the internal/external clocks,

PLLs, CSS and MCO pins.

1. HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or

through the PLL as System clock source.

2. LSI (low-speed internal), 32 KHz low consumption RC used as IWDG

and/or RTC clock source.

3. HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or

through the PLL as System clock source. Can be used also as RTC clock

source.

4. LSE (low-speed external), 32 KHz oscillator used as RTC clock source.

5. PLL (clocked by HSI or HSE), featuring two different output clocks:

- The first output is used to generate the high speed system clock (up to

168 MHz)

- The second output is used to generate the clock for the USB OTG FS

(48 MHz), the random analog generator (<=48 MHz) and the SDIO (<=

48 MHz). 41

Internet/External clock setup

6. PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to

achieve high-quality audio performance on the I2S interface.

7. CSS (Clock security system), once enable and if a HSE clock failure occurs

(HSE used directly or through PLL as System clock source), the System

clock is automatically switched to HSI and an interrupt is generated if

enabled. The interrupt is linked to the Cortex-M4 NMI (Non-Maskable

Interrupt) exception vector.

8. MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL

clock (through a configurable prescaler) on PA8 pin.

9. MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or

PLLI2S clock (through a configurable prescaler) on PC9 pin.

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Example /** @brief System Clock Configuration

* The system Clock is configured as follow :

* System Clock source = PLL (HSE)

* SYSCLK(Hz) = 168000000

* HCLK(Hz) = 168000000

* AHB Prescaler = 1

* APB1 Prescaler = 4

* APB2 Prescaler = 2

* HSE Frequency(Hz) = 8000000

* PLL_M = 8 ( VCO input frequency ranges from 1 to 2 MHz.

VCO = HSE/ PLL_M)

* PLL_N = 336 (set freq. 336 MHz)

* PLL_P = 2 (sysclk = PLL_N/PLL_P but not exceed 168MHz)

* PLL_Q = 7 (USBclk = PLL_N/PLL_Q)

* VDD(V) = 3.3

* Main regulator output voltage = Scale1 mode

* Flash Latency(WS) = 5

* @param None

* @retval None

*/

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static void SystemClock_Config(void)

{

RCC_ClkInitTypeDef RCC_ClkInitStruct;

RCC_OscInitTypeDef RCC_OscInitStruct;

/* Enable Power Control clock */

__PWR_CLK_ENABLE();

/* The voltage scaling allows optimizing the power consumption when the device is

clocked below the maximum system frequency, to update the voltage scaling value

regarding system frequency refer to product datasheet. */

__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1)

;

/* Enable HSE Oscillator and activate PLL with HSE as source */

RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;

RCC_OscInitStruct.HSEState = RCC_HSE_ON;

RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;

RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;

RCC_OscInitStruct.PLL.PLLM = 8;

RCC_OscInitStruct.PLL.PLLN = 336;

RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;

RCC_OscInitStruct.PLL.PLLQ = 7;

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if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)

{

Error_Handler();

}

/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2

clocks dividers */

RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK |

RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 |

RCC_CLOCKTYPE_PCLK2);

RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;

RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;

RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;

RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;

if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)

{

Error_Handler();

}

}

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Simulink Configuration

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Questions?

• Write a program to output clock as follows:

SYSCLK = 160 MHz

PCLK1 = 45 MHz

PCLK2 = 90 MHz

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Boot configuration

• In STM32F10xxx, 3 different boot modes

are provided and can be selected from the

pin.

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Boot mode

• Boot from main flash memory: flash memory is

aliased to address 0x0000 0000, but can also

accessed from address 0x0800 0000

• Boot from system memory: it can be acces from

aliasing address: 0x0000 0000 or 0x1FFF B000

• Boot from embedded SRAM: only at address

0x2000 0000

Note: when booting from SRAM, NVIC exception

table has to be relocated 49

Bit banding

• Bit band operation support allows a single

load/store operation to access a single

data bit

• In ARM Cortex M3, this is supported in two

predefined memory regions call bit-band

regions

• One of them is located in the first 1 MB of

the SRAM and the other is located in the

first 1 MB of the peripheral region

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Bit-band region

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Example of bit-band access

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Data mapping (from bit to word)

Bit_word_address = bit_band_base +

(byte_offset*32) + (bit_number x 4)

Example: To access bit 2 of the byte located

in SRAM address 0x20000300

= 0x22000000 + (0x300*32) + 2*4

= 0x22008008

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Questions?

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