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ARM Cortex-M 系列處理器介紹系列處理器介紹系列處理器介紹系列處理器介紹

以及技術發展趨勢以及技術發展趨勢以及技術發展趨勢以及技術發展趨勢

Leon Chen

ARM Taiwan, Senior FAE

Oct. 14, 2010

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Agenda1. Overview

� Market challenges

� Introducing the family

� Common technology benefits

� Spanning the applications

2. The processors� Cortex-M0

� Cortex-M1

� Cortex-M3

� Cortex-M4

3. Fundamental technologies� Processor core

� Thumb-2 instruction set

� NVIC

� CoreSight

� Ecosystem and CMSIS

4. Development tools and ecosystem

5. Summary

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ARM Cortex-A Series:Applications processors for

feature-rich OS and user applications

ARM Cortex-R Series:Embedded processors for

real-time signal processing

and control applications

ARM Cortex-M Series:Deeply embedded processors

optimized for microcontroller

and low-power applications

Cortex-M processor family� Seamless embedded architecture

� Spanning cost and performance points

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Market challenges

� 8/16-bit running out of performance headroom� As complexity rises so does frequency and memory requirement

� More features at lower cost � Increasing connectivity (e.g. USB, Ethernet, 802.15, NFC)

� Drive for better code reuse

� Analog devices with increasing processing and communication

� Energy efficiency � Wireless sensors, motor control, metering

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Cortex-M processor solution

� Energy efficiency� Lower energy costs

� Ease of use� Lower software costs

� High performance� Competitive products

� Reduced system cost� Lower silicon costs

Low power implementation

Sleep mode support

Wake-up Interrupt Controller

Increased intelligence at node

Broad tools and OS support

Binary compatible roadmap

Pure C target

32-bit RISC architecture

High efficiency processor cores

Integrated Interrupt Controller (NVIC)

Thumb ®-2 code density

Area optimised designs

CoreSight support

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Spanning the application range� Forget traditional 8/16/32-bit classifications

� Seamless architecture across all applications

� Every product optimised for ultra low power systems

Cortex-M0 Cortex-M3 Cortex-M4“8/16-bit” applications “16/32-bit” applications “32-bit/DSC” applications

Lowest cost

Optimised connectivity

Performance efficiency

Feature rich connectivity

MCU plus DSP

Accelerated SIMD, FP & DSP

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Standardization - driven by software reuse � #1 factor in choosing a processor is the software

development tools available for it

Factors considered most important when choosing a microprocessorApril 2005

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� Cortex Microcontroller Software Interface Standard� Abstraction layer for all Cortex-M processor based devices

� Developed in conjunction with silicon, tools and middleware partners

� Benefits to the embedded developer� Consistent software interfaces for silicon and middleware vendors

� Simplifies re-use across Cortex-M processor-based devices

� Reduces software development cost and time-to-market

� Reduces learning curve for new Cortex microcontroller developers

Cortex Microcontroller Standard (CMSIS)

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Addressing proprietary MCU space

� Seamless architecture across all MCU and embedded applications:

Renesas H8

Freescale HCS08

Microchip PIC18

TI MSP4308051

AVR8Infineon C166

Freescale 58xxx

Microchip dsPIC

Microchip PIC24

Renesas SuperH

Atmel AVR32

TI C2000Microchip PIC32

Cortex-M4Cortex-M3Cortex-M0

TI MSP430 Atmel AVR32Infineon C166

Renesas SuperH

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Cortex-M processor industry adoption� ARM Cortex-M3 processor momentum continues

� 35+ licensees in applications from MCU, SoC, wireless sensor nodes

� 140% CAGR in units shipped by vendors

� New ARM Cortex-M0 processor announced in 2009� More than 20 licensees already in MCU, mixed-signal and FSM

replacement

� Cortex-M4 now also available� Released at the end of 2009 with five licensees already including NXP,

ST and TI

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The Products

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� The smallest, lowest power ARM processor� A third of the area and power of ARM7TDMI-S™ processor� 12K gates, 47 µA/MHz on 180ULL in minimal configuration*� 0.9 DMIPS/MHz performance

ARM Cortex-M0 processor

� Significant advantages over 8/16-bit� Longer battery life through energy efficiency� Reduced system cost through code density� Performance headroom for advanced features

� Extends ARM architecture to new applications� Ultra low-power MCU and mixed-signal devices� Ideal sequencer or FSM replacement on SoC� Binary and tools upwards compatible with Cortex-M3 processor

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ARM Cortex-M1 – First for FPGA� First ARM processor specifically optimized for FPGA

� Small, high-frequency soft processor for low-cost volume FPGA� Upwards compatible with Cortex-M3 processor onwards on ASIC/ASSP/MCU� Capable of up to 200MHz on fast FPGA device� Delivers up to 0.8 DMIPS/MHz efficiency from TCM

� Designed for synthesis on multiple FPGA types� Actel ProASIC3, Actel Igloo and Actel Fusion� Altera Cyclone-III, Altera Stratix-III� Xilinx Spartan-3, Xilinx Virtex-5

� 3 Channels to market� Traditional ARM licensing� NEW: Altera/Arrow 1X design start� NEW: Freely available to Actel users

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Cortex-M3 processor - technical excellence

“… . the Cortex-M3 processor will propel us again towa rds a breakthrough in performance, ease of use and qualit y, while also providing a competitive cost structure for our products. We feel that the Cortex M3 processor will play an i mportant role in accelerating the convergence of the MCU mar ket…”

– Jim Nicholas, GM Microcontroller Division, ST

� Optimal performance, high efficiency processor core – 1.25 DMIPS/MHz� Rich, unified Thumb-2 high performance instruction set� Smallest code size and reduced memory requirements

� Integrated bus matrix for increased performance� Advanced power management features and capabilities� Fully configurable to balance features and silicon area� Low latency, integrated Nested Vectored

Interrupt Controller (NVIC)� Sophisticated debug and trace support � Memory Protection Unit (MPU)� Embedded Trace Macrocell (ETM)� Fault Robust Interface

� Launched 2004� Broad adoption within microcontroller

and embedded SoC markets

� Rev2 released in 2008 with many newpower management and configurationcapabilities

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Cortex-M4 for digital signal control

Cortex-M4

MCU

Ease of use

C Programming

Interrupt handling

Ultra low power

DSP

Harvard architecture

Single cycle MAC

Floating Point

Barrel shifter

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Cortex-M4 processor details� ARMv7ME architecture

� Thumb-2 technology� ARMv6 SIMD and DSP� Single cycle MAC (Up to 32 x 32 + 64->64)� Optional decoupled single precision FPU � Integrated configurable NVIC� Compatible with Cortex-M3 processor

� Microarchitecture� 3-stage pipeline with branch speculation� 3x AMBA® AHB-Lite Bus Interfaces

� Configurable for ultra low power � Deep Sleep Mode, Wakeup Interrupt Controller� Power down features for the optional Floating Point Unit

� Flexible configurations for wider applicability� Configurable Interrupt Controller (1-240 Interrupts and Priorities)� Optional Memory Protection Unit, Optional Debug & Trace

Dotted boxes denote optional blocks

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Highest in-class efficiency

Cycle counts on DSP tasks compared, smaller is better

16-bit MCU 32-bit MCU 32-bit Cortex-M4

The Cortex-M4 is ~2X more efficient on most DSP tasks than

leading 16 and 32 bit MCU devices with DSP extensions

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Fundamental Technologies

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Instruction set architecture

Thumb ®

ARM7 ARM9 Cortex-A9Cortex-R4Cortex-M3Cortex-M0

Thumb instruction set upwards compatibility

Cortex-M4

� Thumb� 32-bit operations in 16-bit instructions

� Introduced in ARM7TDMI® processor (‘T’ stands for Thumb)

� Subsequently supported in every ARM processor developed since

� Thumb-2� Enables a performance optimised blend of 16/32-bit instructions

� All processor operations can all be handled in ‘Thumb’ state

� Supported across the Cortex-M processor range

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Instruction set architecture

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Nested Vectored Interrupt Controller

� Faster interrupt response� With less software effort

� ISR written directly in C� Interrupt table is simply a set of

pointers to C routines

� ISRs are standard C functions

� Integrated NVIC handles:� Saving corruptible registers

� Exception prioritization

� Exception nesting

8051 Cortex-M

1. SJMP/L JMP from vector

table to handler

2. PUSH PSW

3. ORL PSW, #00001000b

(to switch register bank)

4. Starting real handler

code

1. Starting real handler

code

Tail-chain

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Code density

Time: 1 clock cycle

Code size: 2 bytes

Time: 8 clock cycles

Code size: 8 bytes

Time: 48 clock cycles*

Code size: 48 bytes

MULS r0,r1,r0 MOV R1,&MulOp1

MOV R2,&MulOp2

MOV SumLo,R3

MOV SumHi,R4

(Memory mapped multiply unit)

MOV A, XL ; 2 bytes

MOV B, YL ; 3 bytes

MUL AB; 1 byte

MOV R0, A; 1 byte

MOV R1, B; 3 bytes

MOV A, XL ; 2 bytes

MOV B, YH ; 3 bytes

MUL AB; 1 byte

ADD A, R1; 1 byte

MOV R1, A; 1 byte

MOV A, B ; 2 bytes

ADDC A, #0 ; 2 bytes

MOV R2, A; 1 byte

MOV A, XH ; 2 bytes

MOV B, YL ; 3 bytes

ARM Cortex-M16-bit example8-bit example (8051)

MUL AB; 1 byte

ADD A, R1; 1 byte

MOV R1, A; 1 byte

MOV A, B ; 2 bytes

ADDC A, R2 ; 1 bytes

MOV R2, A; 1 byte

MOV A, XH ; 2 bytes

MOV B, YH ; 3 bytes

MUL AB; 1 byte

ADD A, R2; 1 byte

MOV R2, A; 1 byte

MOV A, B ; 2 bytes

ADDC A, #0 ; 2 bytes

MOV R3, A; 1 byte

� Cortex-M shows smaller code size than 8/16-bit devi ces� Consider a 16-bit multiply operation

� Required for 10-bit ADC data filtering, encryption algorithms, audio

* 8051 needs at least one cycle per instruction byte fetch as they only have an 8-bit interface

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Cortex-M Processor Power ModesActive mode Leakage + dynamic Running Dhrystone 2.1 benchmark

Sleep mode Leakage + some dynamic Core clock gated, NVIC awake

Deep Sleep mode Leakage only Power still on, most clocks off

Deep Sleep mode State retention (WIC) Most power off, all clocks off

Power off Zero power Power off

Pow

er c

onsu

mpt

ion

Deep Sleep

(WIC)

Sleep

Active

Power Off

Deep Sleep

Not To scale

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Cortex-M low power technologies� All Cortex-M processors are specifically designed for low power, with a

range of complementary technologies including:

� Integrated architectural clock gating

� Sleep and deep sleep modes:� puts the processor into a low-power state with flexible software control

� “Sleep-on-exit” interrupthandling:� enables the

processor to sleepwhenever all outstandingInterrupts are complete

� Wakeup Interrupt Controller(WIC)� enables advanced

interrupt-controlled processing

� enables nW power consumption in deep sleep mode with instant wakeup

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Efficiency with µA to spare� Extremely low power leakage and operation

� 67 µA/MHz active, 7nA state retention in full configuration*� Reduced Flash access and no speculative fetches

� Dramatic energy efficiency advantage over 8/16-bit� Over 2-4x shorter duty cycle than MSP430 and PIC18**� Working smarter, sleeping longer

� Ideal in power optimised designs

* Using ARM Physical IP with PMK on 180ULL process at 1.8V - ARM Cortex-M0 in full configuration (32 interrupts, fast mul, debug)

** Based on benchmarks in public domain. Data from pubic websites0

50

100

150

200

250

300

MS

P43

0

PIC

18L

M0

Active power µA/MHz

Ava

ilabl

e fo

r

your

dev

ice

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Sleep Mode

Low Power Sleep Mode Features

WFI or WFE

Sleep Mode

Active Mode

SLEEPONEXIT bit set

System Level Sleep Possible

Active Mode

Sleep Now

Sleep On Exit

Deep Sleep

Immediate sleep mode entry

Automatic sleep mode entry

on ISR service completion

Communicate to system

that deeper sleep is possible

ISRActive Mode

SLEEPDEEP bit set

Sleep Mode

WFI or WFE

ISR exit

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32-bit Energy Efficiency Advantage

0.1 0.2Time (%)

Pow

er (

mW

)

99.9 100

0.1 % Active Duty

99.9% Sleep

0.3 99.8

0.05 % Active Duty

99.95% Sleep

Average power = 13 µW

Average power = 6.8 µW

47% lower!

9 mW

1 µW

0.1 0.2Time (%)

Pow

er (

mW

)

9 mW

1 µW

99.9 1000.3 99.8

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Optimised Debug with 2-pin SWD

USB

Targeted embedded

systemMicrocontroller

JTAG or Serial

Wire

Cortex-M0 integration

DAP

Cortex-M0JTAG or

Serial Wire

BPU

DWT

BusProcessor

core

ROM /

Flash

SRAM

Peripherals

Additional

test logic

Break Point Unit

Data Watchpoint

Core debug support

(halt, single step, etc)

Debugger access to

memory, peripherals

and optional test

logic

Debug Access Port

Debugger (e.g.

µVision)

In-Circuit Debugger

(e.g. ULINK2)

• The recommended 2 pin debug solution:

• Optimised to access memory mapped debug devices

• Tested and supported with ARM deliverables

• Silicon proven since 2004

• Widely supported by a large debug tool ecosystem

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Cortex Microcontroller Software Interface Standard

� Cortex Microcontroller Software Interface Standard (CMSIS)

� Developed by ARM, silicon and software vendors

� Common interface to peripherals, real-time operating systems, and middleware components

� Defines the basic requirements to achieve software re-usability and portability

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An Example AMBA AHB-Lite System

ARM Processor

On-chip RAM,ROM or FLASH

OptionalExternalMemoryInterface

APBBridge

Timers

Keypad

UART

GPIO

AHB-Lite

APB

� AHB-lite

� Single Master

� Simple Slaves

� No retry or split responses

� Standard AHB modules can be used

� Allows easier module design/debug

� Single clock edge operation

� Uni-directional busses

� No tri-state signals

⇒ Good for synthesis

� Allows burst transfers

� Pipelined operation

Very low gate count for simple systems

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Quick start deliverables� Example AMBA system provided in integration kit

� Fully documented in integration and implementation guide

� Includes example AMBA AHB-lite single master, single layer interconnect

� Includes example GPIO, zero wait-state SRAM/ROM ctrl, PMU components

� Includes C source files for integration test

power control interface

interrupts

AMBA AHB-lite Interconnect

ARM

Cortex-M0

GPIO 0

PMU

ROM

ctrl

SRAM

ctrlGPIO 1GPIO 2

Memory ROM

AHB default slave

Memory SRAM

AHB default slave

GPIO 0

GPIO 1

GPIO 2

AHB default slave

Private Peripheral Bus

Reserved

Example ROM tables

AHB Default Slave0xFFFFFFFF

0xF0001FFF

0xF0000000

0xE0100000

0xE0000000

0x40001800

0x40001000

0x40000800

0x40000000

0x20100000

0x20000000

0x00100000

0x00000000

Example memory mapExample ARM Cortex-M0 AMBA system provided

Reset

Controller

On-chip

RAM

On-chip

ROM

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Development Tools and Ecosystem

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Cortex-M0 mbed Evaluation System

Compile a program online

No Installation!

“Hello World!” in 5 minutes

Very low cost USB / evaluation board

Appears as USB Disklinking to website

Plug it in…

Save to the board andprogram runs!

http://mbed.org/

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ARM Development Products

SoftwareDevelopment

System Simulation

Boards

Target Connection

ASICs and ASSPs MCUs and Smart cards

RVDS 4.0DS-5

MDK-ARMRL-ARM

FastModels

µVision simulator

RVI, RVT2,DSTREAM

ULINK2,ULINKPro

Hardware platforms

Eval boards& MPS

� A summary of all ARM development tool products� All are compatible with the Cortex-M family of processors

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Keil Microcontroller Development Kit (MDK)

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Microcontroller Prototyping System (MPS)

� FPGA hardware platform for Cortex-M

� MPS includes Cortex-M3 and M0 images with a free upgrade to Cortex-M4� Evaluate Cortex-M without a full license

� Save prototyping cost and time

� Comprehensive memory and peripheral subsystem� USB, Ethernet, DVI, MMC/SD, FlexRay/CAN

� User expandable� Use child board interface to develop

custom IP or integrate proven third-party IP and peripheral systems

� Comprehensive development tools� Altera Quartus II (Web Edition)

� Keil MDK-ARM (eval) and ULINK2

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� Superset of standard RealView C Library�Developed for embedded and memory constrained applications

�Optimized for embedded applications

� Minimal overhead for un-used OS functionality

� Un-used functions removed from memory footprint

� Faster system bring-up

� Most functions initialized at point of use

� Up to 92% Reduction in Library Code size� ‘empty main’

�Even more for ‘Hello World’ using printf

MicroLib – optimized C libraries

MicroLib significantly reduces library size in embedded applications

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MicroLib – optimized for embedded

0

5000

10000

15000

20000

25000

ARM Thumb Thumb (M1) Thumb20

5000

10000

15000

20000

25000

30000

ARM Thumb Thumb (M1) Thumb2

Processor Object Standard MicroLib % saving

ARM7TDMI ARM Library Total 21,352 8,980 61%

RO Total 25,608 12,816 51%

ARM7TDMI Thumb Library Total 17,156 6,244 57%

RO Total 20,129 9,348 50%

Cortex-M1 Thumb Library Total 16,452 5,996 64%

RO Total 19,472 9,016 54%

Cortex-M3 Thumb-2 Library Total 15,018 5,796 63%

RO Total 18,616 8,976 54%

Based on Dhrystone 2.1 Benchmark

Library Totals RO Totals

61% 51%

RealView MDK libraries reduce system code size by 50% to 90%

Based on Dhrystone 2.1 Benchmark

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ARM ecosystem for Cortex-M

Over 40,000 members on ARM-based discussion forums

TOOLCHAIN PLATFORMS DEBUGGERS OPERATING SYSTEMS

Quality as well as quantity: Many of these third parties identify ARM related business as ‘largest growth driver’, which means robust, supported

solutions

… and onwards to modeling solutions

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Conclusions� Cortex-M spans the spectrum of embedded application s

� Hardware and software compatibility and reuse

� Drives up energy efficiency� Lower energy costs and longer battery life

� High performance� Enables competitive products

� Reduced system cost� Lower silicon costs and superior

code density

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