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ARM Cortex-M0 system overview

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ARM Cortex-M0 OverviewBy: Daniel Widyanto September 2010

ContentsIntroduction to ARM Cortex-M0 Programmers Model : Processor Modes Programmers Model : Stacks Programmers Model : Core Registers Programmers Model : Interrupts and Exceptions Quizzes

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Introduction to ARM Cortex-M0

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Introduction to ARM Cortex-M0ARM Cortex-M0: Entry-level 32-bit ARM Cortex processor designed for a broad range of embedded applications simple, easy-to-use programmers model highly efficient ultra-low power operation excellent code density deterministic, high-performance interrupt handling upward compatibility with the rest of the Cortex-M processor family

Benefits:

Cortex-M0 core peripherals NVIC:

System Control Block:

An embedded interrupt controller that supports low latency interrupt processing. Provides system implementation information and system control, including configuration, control, and reporting of system exceptions. A 24-bit count-down timer. If implemented, use this as a Real Time Operating System (RTOS) tick timer or as a simple counter4

Optional system timer (SysTick):

Introduction to ARM Cortex-M0 (contd)

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Programmers Model

Processor Modes

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Programmers Model Processor ModesThread mode Used to execute application software. The processor enters Thread mode when it comes out of reset.

Handler mode Used to handle exceptions. The processor returns to Thread mode when it has finished all exception processing.Note: Other ARM architectures support the concept of privileged or unprivileged software execution. This processor does not support different privilege levels. Software execution is always privileged, meaning software can access all the features of the processor.

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Programmers Model

Stacks

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Programmers Model StacksFull descending: stack pointer indicates the last stacked item on the stack memory. Two stacks, two independent stack pointers:Processor mode Thread Handler Used to execute Applications Exception handlers Stack used Main stack or process stack Main stack

Handler mode always uses the MSP (Main Stack Pointer) Thread mode can use MSP (Main Stack Pointer) by default, or PSP (Process Stack Pointer) Controlled by CONTROL register

In an OS environment, ARM recommends that threads running in Thread mode use the process stack and the kernel and exception handlers use the main stack.9

Programmers Model

Core Registers

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Programmers Model Core Registers

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Programmers Model Core RegistersProgram Status Register (PSR) combines: Application Program Status Register (APSR) Interrupt Program Status Register (IPSR) Execution Program Status Register (EPSR) Mutually exclusive each other. User can access the whole registers as PSR, or individual blocks as APSR / IPSR / EPSR, or combination of two blocks

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Programmers Model

Interrupt and Exceptions

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Programmers Model Interrupts and ExceptionsThe vector table is fixed at address 0x00000000 1st record is stack address for MSP The rest of the record are addresses for exception handlers Address only. No instruction such as branch

Address for exception handlers must be in odd value, since ARM Cortex-M0 only supports Thumb mode Bit[0] in address determined whether Thumb mode is used or not

HardFault exception will be triggered for even address.14

Programmers Model Interrupts and ExceptionsException entry ARM Cortex-M0 is automatically save the registers into stack (pointed by MSP) before executing exception handler

The exception handler address then fetch and executed

Exception return

Use BX LR to return the registers value from stack LR defines the mode and stack pointer for the return address: LR = 0xFFFFFFF1: Return to Handler mode, use MSP after return LR = 0xFFFFFFF9: Return to Thread mode, use MSP after return LR = 0xFFFFFFFD: Return to Thread mode, use PSP after return

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Programmers Model Interrupts and ExceptionsDefinition: An event that alters the normal sequence of execution Configurable Priority Synchronous Asynchronous SVCall PendSV, SysTick, IRQ0IRQ31 Unconfigureable Priority HardFault Reset, NMI

Unconfigureable priority exceptions are un-maskable. Configurable priority exceptions are maskable (using PRIMASK) Priority value is 0 (highest) to 192 (lowest) Default priority is 0 (highest) For IRQ0-IRQ31, priority is handled by IPR0 IPR7 register For SVCall, SysTick, and PendSV, priority is handled by SHPR2 SHPR3 register16

Programmers Model Interrupts and ExceptionsMagic words: Tail-chaining On completion of an exception handler, if there is a pending exception that meets the requirements for exception entry, the stack pop is skipped and control transfers to the new exception handler. Happens if the later interrupt has same or lower priority

Late-arriving If a higher priority exception occurs during state saving for a previous exception, the processor switches to handle the higher priority exception and initiates the vector fetch for that exception. State saving is not affected by late arrival because the state saved would be the same for both exceptions. On return from the exception handler of the late-arriving exception, the normal tail-chaining rules apply. Happens if the later interrupt has higher priority

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Programmers Model Interrupts and ExceptionsNVIC: Connecting external peripherals to the core ICER ISER S IRQ [31:0] R ICPR ISPR S R IRQ Pending IPR0IPR7

IRQ Mask*

Prioritize

CPU

*) Mask active means interrupt is enabled18

Quizzes

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QuizzesRun LPCXpresso and download CMSIS example Open core_cm0.h and core_cm0.c file Answer these questions: What assembly instruction that is needed to enable interrupts ? How to set MSP ? (clue: C function name) How to enable specific IRQ ? (clue: C function name) How to set the IRQ priority ? (clue: C function name)

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ARM Cortex-M0 OverviewBy: Daniel Widyanto September 2010

1

ContentsIntroduction to ARM Cortex-M0 Programmers Model : Processor Modes Programmers Model : Stacks Programmers Model : Core Registers Programmers Model : Interrupts and Exceptions Quizzes

2

Introduction to ARM Cortex-M0

3

Introduction to ARM Cortex-M0ARM Cortex-M0: Entry-level 32-bit ARM Cortex processor designed for a broad range of embedded applications simple, easy-to-use programmers model highly efficient ultra-low power operation excellent code density deterministic, high-performance interrupt handling upward compatibility with the rest of the Cortex-M processor family

Benefits:

Cortex-M0 core peripherals NVIC:

System Control Block:

An embedded interrupt controller that supports low latency interrupt processing. Provides system implementation information and system control, including configuration, control, and reporting of system exceptions. A 24-bit count-down timer. If implemented, use this as a Real Time Operating System (RTOS) tick timer or as a simple counter4

Optional system timer (SysTick):

ARM Cortex-M0 have extra peripherals, other than its processing unit core: -NVIC: To control the interrupt -WIC: Wakeup interrupt controller, to wake the MCU from power saving mode without any clock -SysTick: Simple 24-bits timer. This timer can be used as RTOS timer to make the RTOS portable for all of ARM Cortex-M series (Cortex-M0, Cortex-M1, Cortex-M3, Cortex-M4) -Serial Wire Debug (SWD): To enable simple external connection to debug and trace ARM Cortex-M series

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Introduction to ARM Cortex-M0 (contd)

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Programmers Model

Processor Modes

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Programmers Model Processor ModesThread mode Used to execute application software. The processor enters Thread mode when it comes out of reset.

Handler mode Used to handle exceptions. The processor returns to Thread mode when it has finished all exception processing.Note: Other ARM architectures support the concept of privileged or unprivileged software execution. This processor does not support different privilege levels. Software execution is always privileged, meaning software can access all the features of the processor.

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For other ARM Cortex-M series (except ARM CortexM0), the unprivileged mode: has limited access to the MSR and MRS instructions, and cannot use the CPS instruction cannot access the system timer, NVIC, or system control block might have restricted access to memory or peripherals. The Handler mode is always privileged. The Thread mode can be privileged or unprivileged, depending on the settings at CONTROL register. ARM Cortex-M0 retain the mode for compatibility with other ARM Cortex-M series.

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Programmers Model

Stacks

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Programmers Model StacksFull descending: stack pointer indicates the last stacked item on the stack memory. Two stacks, two independent stack pointers:Processor mode Thread Handler Used to execute Applications Exception handlers Stack used Main stack or process stack Main stack

Handler mode always uses the MSP (Main Stack Pointer) Thread mode can use MSP (Main Stack Pointer) by default, or PSP (Process Stack Pointer) Controlled by CONTROL register

In an OS environment, ARM recommends that threads running in Thread mode use the process stack and the kernel and exception handlers use the main stack.9

The MSP and PSP are usually used in RTOS to differentiate application and kernel codes. To simplify the firmware, in ARM Cortex-M0, the PSP can be ignored. User can always use MSP for all of their interrupt handling or normal codes. On reset

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