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  • Cortex-M0 Devices

    Generic User Guide

    Copyright 2009 ARM Limited. All rights reserved.ARM DUI 0497A (ID112109)

  • Cortex-M0 DevicesGeneric User Guide

    Copyright 2009 ARM Limited. All rights reserved.

    Release Information

    The following changes have been made to this book.

    Proprietary Notice

    Words and logos marked with or are registered trademarks or trademarks of ARM Limited in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

    Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

    The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

    This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

    Confidentiality Status

    This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

    Unrestricted Access is an ARM internal classification.

    Product Status

    The information in this document is final, that is for a developed product.

    Web Address

    http://www.arm.com

    Change History

    Date Issue Confidentiality Change

    08 October 2009 A Non-Confidential, Unrestricted Access First release

    ii Copyright 2009 ARM Limited. All rights reserved. ARM DUI 0497ANon-Confidential, Unrestricted Access ID112109

  • ContentsCortex-M0 Devices Generic User Guide

    PrefaceAbout this book ............................................................................................ viiiFeedback ....................................................................................................... xi

    Chapter 1 Introduction1.1 About the Cortex-M0 processor and core peripherals ................................ 1-2

    Chapter 2 The Cortex-M0 Processor2.1 Programmers model .................................................................................... 2-22.2 Memory model .......................................................................................... 2-122.3 Exception model ....................................................................................... 2-192.4 Fault handling ........................................................................................... 2-272.5 Power management .................................................................................. 2-28

    Chapter 3 The Cortex-M0 Instruction Set3.1 Instruction set summary .............................................................................. 3-23.2 Intrinsic functions ........................................................................................ 3-53.3 About the instruction descriptions ............................................................... 3-73.4 Memory access instructions ...................................................................... 3-163.5 General data processing instructions ........................................................ 3-273.6 Branch and control instructions ................................................................. 3-453.7 Miscellaneous instructions ........................................................................ 3-48

    ARM DUI 0497A Copyright 2009 ARM Limited. All rights reserved. iiiID112109 Non-Confidential, Unrestricted Access

  • Contents

    Chapter 4 Cortex-M0 Peripherals4.1 About the Cortex-M0 peripherals ................................................................ 4-24.2 Nested Vectored Interrupt Controller .......................................................... 4-34.3 System Control Block ............................................................................... 4-114.4 Optional system timer, SysTick ................................................................ 4-21

    Appendix A Cortex-M0 OptionsA.1 Cortex-M0 implementation options ............................................................. A-2

    Glossary

    iv Copyright 2009 ARM Limited. All rights reserved. ARM DUI 0497ANon-Confidential, Unrestricted Access ID112109

  • List of TablesCortex-M0 Devices Generic User Guide

    Change History ............................................................................................................. iiTable 2-1 Summary of processor mode and stack use options ................................................ 2-2Table 2-2 Core register set summary ........................................................................................ 2-3Table 2-3 PSR register combinations ........................................................................................ 2-5Table 2-4 APSR bit assignments .............................................................................................. 2-6Table 2-5 IPSR bit assignments ................................................................................................ 2-7Table 2-6 EPSR bit assignments .............................................................................................. 2-8Table 2-7 PRIMASK register bit assignments ........................................................................... 2-9Table 2-8 CONTROL register bit assignments .......................................................................... 2-9Table 2-9 Memory access behavior ........................................................................................ 2-15Table 2-10 Memory region shareability and cache policies ...................................................... 2-15Table 2-11 Properties of the different exception types .............................................................. 2-20Table 2-12 Exception return behavior ....................................................................................... 2-26Table 3-1 Cortex-M0 instructions .............................................................................................. 3-2Table 3-2 CMSIS intrinsic functions to generate some Cortex-M0 instructions ........................ 3-5Table 3-3 CMSIS intrinsic functions to access the special registers ......................................... 3-6Table 3-4 Condition code suffixes ........................................................................................... 3-15Table 3-5 Memory access instructions .................................................................................... 3-16Table 3-6 Data processing instructions ................................................................................... 3-27Table 3-7 ADC, ADD, RSB, SBC and SUB operand restrictions ............................................ 3-31Table 3-8 Branch and control instructions ............................................................................... 3-45Table 3-9 Branch ranges ......................................................................................................... 3-46Table 3-10 Miscellaneous instructions ...................................................................................... 3-48

    ARM DUI 0497A Copyright 2009 ARM Limited. All rights reserved. vID112109 Non-Confidential, Unrestricted Access

  • List of Tables

    Table 4-1 Core peripheral register regions ............................................................................... 4-2Table 4-2 NVIC register summary ............................................................................................ 4-3Table 4-3 CMSIS access NVIC functions ................................................................................. 4-3Table 4-4 ISER bit assignments ............................................................................................... 4-4Table 4-5 ICER bit assignments ............................................................................................... 4-5Table 4-6 ISPR bit assignments ............................................................................................... 4-6Table 4-7 ICPR bit assignments ............................................................................................... 4-6Table 4-8 IPR bit assignments .................................................................................................. 4-7Table 4-9 CMSIS functions for NVIC control .......................................................................... 4-10Table 4-10 Summary of the SCB registers ............................................................................... 4-11Table 4-11 CPUID register bit assignments .............................................................................. 4-12Table 4-12 ICSR bit assignments ............................................................................................. 4-13Table 4-13 AIRCR bit assignments ........................................................................................... 4-16Table 4-14 SCR bit assignments .............................................................................................. 4-17Table 4-15 CCR bit assignments .............................................................................................. 4-18Table 4-16 System fault handler p

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