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  • UM10503LPC43xx ARM Cortex-M4/M0 multi-core microcontroller Rev. 1.8 28 January 2014 User manual

    Document informationInfo ContentKeywords LPC43xx, LPC4300, LPC4370, LPC4350, LPC4330, LPC4320, LPC4310,

    LPC4357, LPC4353, LPC4337, LPC4333, LPC4327, LPC4325, LPC4323, LPC4322, LPC4317, LPC4315, LPC4313, LPC4312, ARM Cortex-M4, ARM Cortex-M0, SPIFI, SCT, USB, Ethernet, LPC4300 user manual, LPC43xx user manual

    Abstract LPC4300 user manual

  • NXP Semiconductors UM10503LPC43xx User manual

    Revision historyRev Date Description

    1.8 20140128 LPC43xx User manual

    Modifications: Description of the C_CAN CLKDIV register corrected. See Table 1073. Priorities of the EMC SDRAM ports added. See Section 22.4. Table 20 OTP function allocation corrected. Table 12 OTP bank programming API functions available in ROM added. Bit field width of bits LEVEL in the FIFO_STS and bits FIFO_LEVEL in the FIFO_CFG register

    changed to 4 bits. See Table 1120 and Table 1121. Description of the FIFO_STS register updated to explain the use of the LEVEL bits. See Table 1120.

    Condition for the CAN PCLK added: PCLK < 50 MHz. See Section 44.2. VBUS connection requirement for self-powered USB0 added to Section 24.5.1 Requirements for

    connecting the USB0_VBUS/USB1_VBUS signal. SRAM memory location retained in Power-down mode clarified in Section 3.3.5 Memory retention in

    the Power-down modes and Figure 6 Flashless parts: System memory map (see Figure 7 for detailed addresses of all peripherals).

    Section 36.7.1 Register read procedure updated for reading the RTC registers after wake-up. RTC_ALARM pin description corrected (Table 871 RTC pin description). This pin is not a 1.8 V pin. Part LPC4350FBD208 removed. Read-only status bits for EMC clock divider register configuration register added. See Table 161

    CCU1 branch clock configuration register (CLK_M4_EMCDIV_CFG, addresses 0x4005 1478) bit description.

    Description of the WAKEUP bits expanded in the CCU branch clock configuration and status registers. See Section 13.5.3 CCU1/2 branch clock configuration registers and Section 13.5.4 CCU1/2 branch clock status registers.

    Bit RUN_N added to CCU branch clock status registers. See Section 13.5.3 CCU1/2 branch clock configuration registers.

    Statement added: Only write to the RTC registers when the 32 kHz oscillator is running. See Section 36.2. Same for Alarm timer. See Section 35.2.

    MII availability clarified: Ethernet MII not available on LQFP144 and TFBGA100 parts. See Section 27.1 How to read this chapter.

    Timer input and output connections clarified in Section 31.2 and Figure 39 Connections between GIMA and peripherals.

    Section 44.7.5.2 Calculating the C_CAN bit rate added.

    UM10503 All information provided in this document is subject to legal disclaimers. NXP B.V. 2014. All rights reserved.

    User manual Rev. 1.8 28 January 2014 2 of 1420

  • NXP Semiconductors UM10503LPC43xx User manual

    1.7 20131017 LPC43xx User manual

    Modifications: 12-bit ADC (ADCHS) for parts LPC4370 added. See Chapter 47. Table LPC43xx part identification numbers updated. BASE_APLL_CLK renamed to BASE_AUDIO_CLK in Chapter 12 LPC43xx Clock Generation Unit

    (CGU), Chapter 13 LPC43xx Clock Control Unit (CCU), Chapter 10 LPC43xx Configuration Registers (CREG), and Chapter 43 LPC43xx I2S interface.

    Core M0SUB added for parts LPLC4370. See Chapter 2 LPC43xx Multi-Core configuration and Inter-Process Communication (IPC), Chapter 12 LPC43xx Clock Generation Unit (CGU), Chapter 13 LPC43xx Clock Control Unit (CCU), Chapter 10 LPC43xx Configuration Registers (CREG), Chapter 14 LPC43xx Reset Generation Unit (RGU), and Chapter 3 LPC43xx Memory mapping.

    Power-down mode with M0SUB SRAM maintained added for parts LPC4370. See Chapter 11 LPC43xx Power Management Controller (PMC) and Table 115.

    AES speed corrected. Bit description of register CREG5 corrected. Bits 9:0 changed to reserved. Use bits 12:10 for

    disabling JTAG. See Section 10.4.3 CREG5 control register. Description of the RESET pin updated in Section 15.2 Pin description. Use of EMC_CLK pins clarified for SDRAM devices. See Section 22.2. Pin description of the RESET pin updated. Pin description of pins SD_VOLTD[2:0] updated. Add bits 20 (BOD reset) and 21 (reset after wake-up from deep power-down) to the event router

    registers. Table 200 SD/MMC delay register (SDDELAY, address 0x4008 6D80) bit description added. USB driver code listing corrected. See Section 26.5 USB API. Register RESET_EXT_STAT4 removed. SDRAM address mappings added. Device MX25L6435EM2I-10G added to Table 24 QSPI devices supported by the boot code and the

    SPIFI API. Table 4 Ordering options corrected. ULPI not available on 144-pin and 100-pin packages. Editorial updates to Section 5.3.5 Boot image creation and Figure 16 Image encryption flow

    added. Editorial edits to Chapter 7 LPC43xx Security API. Section CMAC using AES hardware

    acceleration removed. VADC replaced by ADCHS throughout the document. Section 12.2.1 Configuring the BASE_M4_CLK for high operating frequencies corrected to ensure

    safe operation of the clock ramping procedure. Figures and tables in Section 43.7.2 I2S operating modes corrected.

    Revision history continuedRev Date Description

    UM10503 All information provided in this document is subject to legal disclaimers. NXP B.V. 2014. All rights reserved.

    User manual Rev. 1.8 28 January 2014 3 of 1420

  • NXP Semiconductors UM10503LPC43xx User manual

    Modifications: LPC4320 and LPC4310 part IDs corrected. See Table 45 LPC43xx part identification numbers and the LPC4350/30/20/10 errata sheet.

    Description of word1 of the part id corrected. See Table 45 LPC43xx part identification numbers. General description of the OTP updated. General description of the AES updated. Figure 14 Boot process for parts without flash updated. Figure 115 Repetitive Interrupt Timer (RIT) block diagram corrected. Details about encryption of the image header added in Section 5.3.4 Boot image header format. Figure 14 Boot process for parts without flash corrected. SPI(SSP) boot requires image header. Bit description of Table 378 Debounce Count Register (DEBNCE, address 0x4000 4064) bit

    description updated. Host clock is the SD_CLK clock. Security features updates. FIPS compliancy added. ISP mode added to Figure 14 Boot process for parts without flash. Reset values of the EEPROM RWSTATE and WSTATE registers updated. AES API function offsets corrected. Part MX25L8006EM2L-12GMX25L8035E, MX25L1633E, MX25L3235E, MX25L6435E,

    MX25L12835F, MX25L25635F added to list of devices supported for SPIFI boot.

    1.6 20130125 LPC43xx user manual.

    Modifications: SGPIO-DMA connections clarified. SGPIO location corrected. SGPIO added to DMA master 0. GPIO group interrupt wake-up from power-down modes corrected. Only wake-up from sleep mode

    supported. Section Supported QSPI devices moved to Chapter LPC43xx Boot ROM. SPIFI register map and register descriptions added in Chapter LPC43xx SPI Flash Interface

    (SPIFI). Bit description of Table CAN error counter (EC, address 0x400E 2008 (C_CAN0) and 0x400A 4008

    (C_CAN1)) bit description corrected. Bit clock calculation and bit description corrected in Section CAN bit timing register.

    Revision history continuedRev Date Description

    UM10503 All information provided in this document is subject to legal disclaimers. NXP B.V. 2014. All rights reserved.

    User manual Rev. 1.8 28 January 2014 4 of 1420

  • NXP Semiconductors UM10503LPC43xx User manual

    1.5 20121203 LPC43xx user manual.

    Modifications Statement regarding the connection between sampling pin P2_7 and the watchdog timer overflow bit is incorrect and was removed in Section Sampling of pin P2_7 and Figure Boot process flowchart for LPC43xx parts with flash.

    SCT alias register locations corrected. IRC accuracy corrected for flash-based parts. SCT with dither engine added for flash-based parts. SGPIO DMA connections added in Table DMA mux control register (DMAMUX, address 0x4004

    311C) bit description. Section MAC Frame filter register updated to include hash filter option. Section Hash filter with examples added. Description of the I2C MASK register clarified. Description of the I2C slave address updated. UART1 TER register location and bit description corrected. Polarity of the DMACSYNC bit in the GPDMA SYNC register corrected. SGPIO pattern match example corrected. OTP API function table corrected. Location 0x1C is reserved. SPIFI data rate and maximum clock corrected to SPIFI_CLK = 104 MHz and 52 MB/s. Parts LPC433x, LPC432x, and LPC431x added. The following changes were made on the TFBGA180 pinout:

    P1_13 moved from ball D6 to L8. P7_5 moved from ball C7 to A7. PF_4 moved from ball L8 to D6. RESET moved from ball B7 to C7. RTCX2 moved from ball A7 to B7. Ball G10 changed from VSS to VDDIO.

    Section JTAG TAP Identification updated. EMC Configuration register, bit 8 changed to reserved. See Table EMC Configuration register

    (CONFIG - address 0x4000 5008) bit description. Dual-core power-down modes added to Chapter LPC43xx Power Management Controller (PMC).

    Revision history continuedRev Date Description

    UM10503 All information provided in this document is subject to legal disclaimers. NXP B.V. 2014. All rights reserved.

    User manual Rev. 1.8 28 January 2014 5 of 1420

  • NXP Semiconductors UM10503LPC43xx User manual

    Modifications: ETM time stamping feature not implemented. Bit 0 in the RGU RESET_STATUS0 register changed to reserved. Section Determine the cause of a

    core reset added. Micron part N25Q256 removed from the list of devices

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