derivation of logical effort

UNIVERSITA DEGLI STUDI DI ROMA “LA SAPIENZA”

DERIVATION OF THE LOGICAL EFFORT METHOD

Curse: Architecture of integrated systems Vol. II

Reneé J. Quintero C.1273644

METHOD OF LOGICAL EFFORT

The method is an easy way to stimate delay in a CMOS circuit and specifies the proper number of logic stages on a path and the best transistors sizes for the logic gates.

How fast can be implemented a circuit in terms of :

Topology Selection

Gate Sizing

TIME BECOMES CRITICAL!!!

Simulate and tweak Very time consuming

A systematic approach is needed

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d = gh + p

MODEL OF A LOGIC GATE

Electrical model that approximates the behavior of a single static CMOS logic gate

VDD

in

Cin

Rpun

Rpdn

Cpi

Out

Cout

The logic gate is modeled by: Cin, Rpun,Rpdn,Cpi


The widths of all transistor are scaled by a factor of α, on the template version of the circuits, and the resistance are modeled equal.

Cin: Capacitance of the transistor gate connected to the input terminal

Cpi: Parasitic capacitance

Cout: Load capacitance

Rpun: Pullup resistance

Rpdn: Pulldown resistance

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Cin = α ⋅Ct

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Cpi = α ⋅Cpt

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Ri = Rpun = Rpdn =Rtα

Cpt and Ct are the equivalents to the parasitic capacitance and the input capacitance, respectively.


in Out

Wp/Lp

Wn/Ln

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Ct = k1⋅Wn ⋅ Ln + k1⋅W p ⋅ Lp

A design for an inverter is given with the transistors labeled with the ratio of the width to length of the transistor

The capacitance formed by the gates of both transistors:

This capacitance loads the input signal.


The resistances are determined by:

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1

Rt=k2⋅ μn ⋅Wn

Ln=k2⋅ μ p ⋅W p

Lp

The constants ki depends on the fabrication process and μ’s characterize the relative mobilities of carriers in n-type and p-type transistors.

To ensure Rpup= Rpdn :

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μn ⋅Wn

Ln=μ p ⋅W p

Lp

DELAY IN LOGIC GATE

Meanly causes of the delay on a logic gate

Load on the gate’s output f

Parasitic Delay p

Stage Effort

Logical Effort g Electrical Effort h

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f = gh

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h =Cout /Cin

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d = f + p Fixed Value

Depends on the load and properties of the logic gate

DELAY IN LOGIC GATE

The method quantifies these effects to simplify delay analysis for individual logic gates and multistage logic networks.

The delay is expressed in terms of τ, expressing an absolute delay:

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dabs = dτ

The model describes delay cause by:• The capacitive load that the logic gate drives• The topology of the logic gate

τ: Delay of an inverter driving an identical inverter with no parasitics

DELAY IN LOGIC GATE

The delay is just the RC delay associated with charging and discharging the capacitance attached to the output node

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dabs = k⋅ Ri⋅ Cout +Cpi( ) = k⋅Rtα

⎛

⎝ ⎜

⎞

⎠ ⎟⋅Cin ⋅

Cout

Cin

⎛

⎝ ⎜

⎞

⎠ ⎟+ k⋅

Rtα

⎛

⎝ ⎜

⎞

⎠ ⎟⋅ α ⋅Cpt( )

dabs = (k⋅ Rt ⋅Ct )⋅ (Cout

Cin

) + k⋅ Rt ⋅Cpt

VDD

in

Cin

Rpun

Rpdn

Cpi

Out

Cout

DELAY IN LOGIC GATE

To obtain the key equations of logical effort

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dabs = τ ⋅ (g⋅ h + p)

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τ =k⋅ Rinv ⋅Cinv

dabs: Delay of the logic gate

τ: Represent the speed of the basic transistors

Cinv: Input Capacitance of the inverter

Rinv: Resistance of the pullup or pulldown transistor in the inverter

g: Logical effort. Determined by the circuit topology of the template for the logic gate, and is independent of α. Expresses the effects of circuit topology on the delay free of considerations of loading/transistor size. It’s defined so that an inverter has logical effort of 1.

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g =Rt ⋅Ct

Rinv ⋅Cinv

DELAY IN LOGIC GATE

The equation of dabs handles both the linear and saturated regions of the transistor behavior, making the method valid for both cases

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h =Cout

Cin

p =Rt ⋅Cpt

Rinv ⋅Cinv

h: Electrical effort. Determines the gate’s input capacitance. The size of the transistors influences it. Combines the effects of the external load, establish Cout, with the size of the transistors in the logic gate, which establish Cin

p: Parasitic delay of the logic gate, which is independent of the logic gate’s scale α, representing a fixed delay associated with the operations of the gate. Intrinsic delay of the gate due to its own internal capacitance, independent of the size of the transistor

DELAY IN LOGIC GATE

The total delay, measured in units of τ:

The parasitics delays are given as multiples of the parasitic delay of an inverter pinv Linear Relationship

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d = f + p

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d = g⋅ h + p⋅ pinv

The slope of each line is the logical effort of the gate. The delay can be adjusted chaging the electrical effort or the logic gate, having a different logical effort. The parasitics delay stay fixed once the gate is chosen.

DELAY IN LOGIC GATE

MULTISTAGE LOGIC NETWORKS

This method allows to obtein the best number of stages in a multistage network.

The path delay D is the sum of the delays of each of the stages of logic in the path.

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D = Σdi = DF + P


• Path Effort Delay

• Path Parasitic Delay

Path logical Effort

Path Electrical EffortCapacitance of the path as a whole

A new kind of effort must be introduced to account for fanout within a network.

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D f = gi⋅ hi∑

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H =Cout

Cin

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G = gi∏

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P = pi∑


In a network the current of the drive may be directed along the path and off the path Branching Effort b

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b =Conpath +Coffpath

Conpath

=Ctotal

Cuseful

Connections that lead off the path

Path that we are studying


• Branching effort along the path

• Path effort Holds the key for minimizing the delay. Depends only on the circuit topology and loading not on the sizes of the transistors used.

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B⋅H =Cout

Cin

⋅ bi∏ = hi∏

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B = bi∏

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F =GBH• Path branching and electrical efforts are related to the electrical effort of each stage:


PRINCIPLE: The path delay is least when each stage in the path bears the same stage effort.

Minimum stage effort must be:

Minimum delay achievable along a path:

To achive the transistor size according to the minimun delay, each logic stage should be designed with electrical effort:

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Dm = NF1/N + P

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fm = gihi = F1/N

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hmi =F1/N

gi


This equation can be solve to determine the number of stages Nm, that achieves minimun delay.The extra delay incurred by using the wrong number of stages is small unless the error in the number of stages is large.

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Dm = NF1/N + P

Determine the size of the transistor using the capacitances along the path

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Cin i=gi⋅Cout i

fm

MINIMIZING DELAY ALONG A PATH

Gate1

Gate2

C3

Input Capacitance: C1 and C2

Logical Effort: g1 and g2

Parasitic delay: p1 and p2

The total delay, measured in units of τ

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D = (g1⋅ h1⋅ p1) + (g2⋅ h2 + p2)

The delay model for a single logic gate leads to a method for minimizing the delay in a sequence of logic gates connected in series.


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h1 =C2

C1

h2 =C3

C2

h1⋅ h2 =C3

C1

= H

The Branching effort is 1, in the figure and H is a constant that cannot be adjust.

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h2 =H

h1

D = (g1⋅ h1 + p1) + (g2⋅Hh1

+ p2)

The logical efforts g1 and g2 and parasitic delays p1 and p2 in this equation are fixed, the electrical efforts can be adjusted to find the minimization.


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∂D∂h1

= g1 −g2⋅Hh1

2 = 0

g1⋅ h1 = g2⋅ h2

This result generalizes to paths with any number of stages and to paths that include branching effort. The fastest design always equalizes effort in each stage.

To minimize D take the partial derivative with respect the only variable h1:

Delay is minimized when each stage bears the same efforts. This is independent of the scale of the circuits and of the parasitics delays.

It does not say that the delays in the two stages will be equal, the delays will differ if the parasitics delays differ.


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h1h2 ....hN = BH

g1g2....gN =G

(g1h1)(g2h2)....(gNhN ) =GBH = F

Compute of the effort in each stage, for a path of length N

To obtain minimum delay, the N factors on the left must be equal, so that each stage bears the same effort fm


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fmN = F

fm = F1/N

hi =fmgi

To calculate transistor sizes, we work backward or forward along the path, choosing sizes to obtain the required electrical effort in each stage.fm : determine the best stage effort when the number of stages, N, is know.

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Dm = Σ(gihi + pi) = NF1/N + P

MINIMUN PATH DELAY

MINIMUM NUMBER OF STAGES

Delay can be reduced by adjusting the number of stages in the path.

Consider:

n1: Stages of the path of logic gates.

n2: Additional inverters to the path. This can be

altered if necessary.

N = n1 + n2 Total number of stages

Path Effort F = GBH is know, the logical and branching efforts are properties of the n1 logic stages that will not be altered by adding inverters, and the electrical effort is determined by the input and load capacitances required.


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Dm = NF1/N + ( pii=1

n1

∑ ) + (N − n1)pinv

Delay obtained distributing effort equally among the N stages

Parasitic delay of the logic stages

Parasitic delay of the inverters

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∂Dm

∂N= −F1/N ln(F1/N ) + F1/N + pinv = 0


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ρ =F1/Nm

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pinv + ρ (1− lnρ) = 0

Best stage effort

Solution of the equation

ρ: is a constant independent of the properties of the path, represent the stage effort that will result when a path uses the number of stages required to achieved least delay.


Sensitivity of the delay to the number of stages

LIMITATIONS OF THE METHOD

The simplicity of the method results in a number of limitations:

• The linear delay model fails to capture the effect of input slope.

• Logical effort does not account for interconnect. It is most applicable to high-speed circuits with regular layouts where routing delay does not dominate.

• The method doesn’t explain how to design for minimum area or power given a fixed speed constraint.

• Paths with complex branching are difficult to analyze by hand.

CONCLUSIONS

• Facilitates comparison of different circuit topologies.• Easily select gate sizes for minimum delay.• Circuits are faster when effort delays of each stage

are equal. • Path delay is insensitive to modest deviations from

optimal sizes.• Can be applied to different kinds of logic: Domino,

Nora, Transmision Gates, and others.

REFERENCES

• I. Sutherlan, B. Sproull, D. Harris, “Logical Effort: Designing Fast CMOS Circuits”, Morgan Kaufmann Publishers, Inc.

• N.H.E.Westw, D. Harris, “CMOS VLSI Design: A circuits and systems perspective”, Pearson – Addison Wesley.

• M. Olivieri, “Elementi di progettazione dei sistemi VLSI: Architetture, circuiti e metodi. Vol II”, Edises.

derivation of logical effort

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