advd lecture 7 logical effort
TRANSCRIPT
Digital VLSI Design
• Full Automation• Maximum benefit of scaling• High speed ,• low power• Robustness
• Full Automation• Maximum benefit of scaling• High speed ,• low power• Robustness
Need of simple delay model
• Delay depends on many factors—charge,discharge, parasitic, w/L, fan in- fanout,topology
• Existing delay models do not give clearindication of contribution of each factor
• Circuit designers waste too much timesimulating and tweaking circuits
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• Delay depends on many factors—charge,discharge, parasitic, w/L, fan in- fanout,topology
• Existing delay models do not give clearindication of contribution of each factor
• Circuit designers waste too much timesimulating and tweaking circuits
Using LE in design of inverterchain
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Using LE in design of inverterchain
CKT DESIGN PROBLEMS
• Chip designers face a bewildering array ofchoices.
• What is the best circuit topology for afunction?
• How large should the transistors be?• How many stages of logic give least
delay?
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• Chip designers face a bewildering array ofchoices.
• What is the best circuit topology for afunction?
• How large should the transistors be?• How many stages of logic give least
delay?
Need of simple delay model
• Circuit designers waste too much time
simulating and tweaking circuits
• High speed logic designers need to know
where time is going in their logic
• CAD engineers need to understand
circuits to build better tools5
• Circuit designers waste too much time
simulating and tweaking circuits
• High speed logic designers need to know
where time is going in their logic
• CAD engineers need to understand
circuits to build better tools
Delay in a Logic Gate
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Delay contributors
• τ is speed of basic transistor
• p-intrinsic delay of the gate due to its own
internal capacitances
• h—combines the effect of external load
with sizes of transistors
• g– effect of circuit topology7
• τ is speed of basic transistor
• p-intrinsic delay of the gate due to its own
internal capacitances
• h—combines the effect of external load
with sizes of transistors
• g– effect of circuit topology
Observations• Logical effort describes relative ability of gate
topology to deliver current [defined to be 1(bestav. of charge and discharge both] for aninverter)
• Electrical effort is the ratio of output to inputcapacitance
• Delay increases with electrical effort• Delay increases ---More complex gates have
greater logical effort and parasitic delay
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• Logical effort describes relative ability of gatetopology to deliver current [defined to be 1(bestav. of charge and discharge both] for aninverter)
• Electrical effort is the ratio of output to inputcapacitance
• Delay increases with electrical effort• Delay increases ---More complex gates have
greater logical effort and parasitic delay
Estimation of Estimation of
CMOS Ring Oscillator Circuit• An odd number of inverter circuits
connected serially with outputbrought back to input will be astableand can be used an an oscillator(called a ring oscillator)
• Ring oscillators are typically used tocharacterize a new technology as toits intrinsic device performance
• Frequency and stage are related asfollows:
f = 1/T = 1/(2nP)where n is the number of stagesandP is the stage delay
• An odd number of inverter circuitsconnected serially with outputbrought back to input will be astableand can be used an an oscillator(called a ring oscillator)
• Ring oscillators are typically used tocharacterize a new technology as toits intrinsic device performance
• Frequency and stage are related asfollows:
f = 1/T = 1/(2nP)where n is the number of stagesandP is the stage delay
Ring Oscillator—COMPARINGDIFFERENT TECHNOLOGIES
v0 v1 v5
v1 v2v0 v3 v4 v5
v0 v1 v5
v1 v2v0 v3 v4 v5
T = 2 t p N 2 N tp >> tf +tr
Computing Logical Effort
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Different gates
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Observations
• More complex gates have larger logicalefforts
• Logical efforts grow with increase in no. ofinputs
• Complex gates exhibit high g, greaterdelay
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• More complex gates have larger logicalefforts
• Logical efforts grow with increase in no. ofinputs
• Complex gates exhibit high g, greaterdelay
Parasitic delay
• It is fixed for a gate• More complex gate—higher parasitic delay• Ref. Pinv=1 (inverter parasitic delay )• For other gates , parasitic delay is written
in terms of pinv
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• It is fixed for a gate• More complex gate—higher parasitic delay• Ref. Pinv=1 (inverter parasitic delay )• For other gates , parasitic delay is written
in terms of pinv
Parasitic delay
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How to compute Pinv• For inv. g=1, dabs= τ(h+pinv)• In a given tech., plot d vs. h• Plot would be st. line with slope τ, & intercept-
(pinv × τ)• Pinv can be estimated after obtaining τ• Draw similar plot for other gates• Once τ is obtained , g and p of other gates can
be found out.
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• For inv. g=1, dabs= τ(h+pinv)• In a given tech., plot d vs. h• Plot would be st. line with slope τ, & intercept-
(pinv × τ)• Pinv can be estimated after obtaining τ• Draw similar plot for other gates• Once τ is obtained , g and p of other gates can
be found out.
Delay equation plot
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Choice Of Standard Reference
Calculating delay of an inverter
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Delay of 2 input Nand gate
Delay of 2 input NOR gate
MINIMUM POSSIBLE DELAY
Computing Intrinsic TransistorCapacitance
• Intrinsic PN junction capacitance of thedriving circuit must be added to the loadcapacitance Cload
• Consider the inverter example at left:– Area and perimeter of the PMOS and
NMOS transistors are calculated fromthe layout and inserted into the circuitmodel
• NMOS drain area = Wn x Ddrain
• PMOS drain area = Wp x Ddrain
• NMOS drain perimeter = 2 (Wn + Ddrain)• PMOS drain perimeter = 2 (Wp + Ddrain)
• SPICE simulations were done (bottomleft) for a fixed extrinsic load of 100fFwith increasing transistor width (Wp/Wn= 2.75)
– Results show diminishing returnsbeyond a certain Wn (say about 6 um)due to effect of the increasing draincapacitance on the overall capacitiveload
• Intrinsic PN junction capacitance of thedriving circuit must be added to the loadcapacitance Cload
• Consider the inverter example at left:– Area and perimeter of the PMOS and
NMOS transistors are calculated fromthe layout and inserted into the circuitmodel
• NMOS drain area = Wn x Ddrain
• PMOS drain area = Wp x Ddrain
• NMOS drain perimeter = 2 (Wn + Ddrain)• PMOS drain perimeter = 2 (Wp + Ddrain)
• SPICE simulations were done (bottomleft) for a fixed extrinsic load of 100fFwith increasing transistor width (Wp/Wn= 2.75)
– Results show diminishing returnsbeyond a certain Wn (say about 6 um)due to effect of the increasing draincapacitance on the overall capacitiveload
MINIMUM DELAY ~ ZERO DELAY
R= Wp/Wn
Non zero value
Area x Delay Figure of Merit• Increasing device width shows
diminishing returns on propagationdelay time
• Define a figure of merit as area x delayfor the inverter circuit
– Increasing device width Wn shows aminimum in area x delay product
• Unconstrained increase in transistorwidth in order to improve circuit delayis often a poor tradeoff due to the highcost of silicon real estate on the wafer!!
• Increasing device width showsdiminishing returns on propagationdelay time
• Define a figure of merit as area x delayfor the inverter circuit
– Increasing device width Wn shows aminimum in area x delay product
• Unconstrained increase in transistorwidth in order to improve circuit delayis often a poor tradeoff due to the highcost of silicon real estate on the wafer!!
Design a chain of inv. for min delay
T-network Delay Model Of wire
• Star-delta-transformation• Vout=ZBC/(ZAB+ZBC)• Vout=[(2/RC)/(S+2/RC)]*(1/S)• =(1/s)-1/(s+2/RC)• =U(t)[1-exp(-2/RC)t]• FOR V50% delay• tp=(RC ln2)/2=0.35 RC
• Star-delta-transformation• Vout=ZBC/(ZAB+ZBC)• Vout=[(2/RC)/(S+2/RC)]*(1/S)• =(1/s)-1/(s+2/RC)• =U(t)[1-exp(-2/RC)t]• FOR V50% delay• tp=(RC ln2)/2=0.35 RC
Delay in the presence of long wires
Design Of Inverter Chain
For Min. Delay
Sizing a path for minimum delay
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Branching effort along a path
→ Used for sizingfor delay
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Where BH is
→ Used for sizingfor delay
Observations regarding F
• F depends on only topology and loading
• F is Indep. of transistor sizes
• F is unchanged if inverters are added orremoved
EE141 36
• F depends on only topology and loading
• F is Indep. of transistor sizes
• F is unchanged if inverters are added orremoved
Path Delay D
• Sum of delay of all stages
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Condition for min. path delay
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On Differentiation:
Thus, minimum stage effort of each stage reqd. formin. delay along a path is
We shd. choose transistorsizes such that stage effortis same for all blocks
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Thus, minimum delay achievable along a path is
We shd. choose transistorsizes such that stage effortis same for all blocks
Example
Compute foreach stage
Apply capacitance transformation backwards
i
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Apply capacitance transformation backwards
Chain Of Inverters
C2C1
Ci
CL
1 u u2 uN-1
In Out
uopt = e
C2C1
Ci
CL
1 u u2 uN-1
In Out
uopt = e
Optimizing no of stages in a pathfor min. delay
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To find optimum N
EE14144If pinv = 0,
For Ň stages in chain with invertersBest delay per stage , d = gh + pinv
d = ρ + pinv
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For Ň stages in chain with invertersBest delay per stage , d = gh + pinv
d = ρ + pinv
Graphical solAs pinv grows, adding inverters become less advantageous
EE14146
Chain Of Inverters— BEST NO OF STAGES
C2C1
Ci
CL
1 u u2 uN-1
In Out
uopt = e
C2C1
Ci
CL
1 u u2 uN-1
In Out
uopt = e
Chain Of Inverters— BEST NO OF STAGES
C2C1
Ci
CL
1 u u2 uN-1
In Out
uopt = e
gu= gav x [2 µ / (γ+μ)]
gd= gav x [2 γ / (γ+μ)]
C2C1
Ci
CL
1 u u2 uN-1
In Out
uopt = e
For large N, delay expression-
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For ρ = 4Ď = log 4F X FO4
Where FO4 = fanout of 4 inverter delay
FO4 DELAY
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HERE ρ = gh = 1 x 4 = 4; so d = 5τ
Thus for ρ = 4Ď = log 4F X FO4 inverter delay
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Wrong no of stages
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EE14153
Wrong size, L=1
Ρ=4
W 4sW 16 W
C=1 C=4s C=16
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Mis-sized
Ρ=4Ρ=4/ sΡ= 4s
D = ∑gh + ∑pinv= (4s + 4/s + 4 ) + 3 pinv= 15 units (s=1)
EE14155