1 microelettronica logical effort and delay lection 4
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MICROELETTRONICA
Logical Effort and delay
Lection 4
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Outline
• Introduction
• Delay in a Logic Gate
• Multistage Logic Networks
• Choosing the Best Number of Stages
• Example
• Summary
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Introduction
• The designer faces many choices:
– What is the best topology for a function in order to have the least delay?
– How wide should the transistor be?
• The logical effort method helps to make these decisions– Uses a simple linear model for the delay– Allows simple calculations and comparison of
alternatives
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Delay in a Logic Gate
• Express delays in process-independent unit
absdd
τ= 3RC
12 ps in 180 nm process 40 ps in 0.6 μm process
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Delay in a Logic Gate
• Express delays in process-independent unit
• Delay has two components
• Effort delay f = gh (. stage effort)
• Parasitic delay p
absdd
d pf
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Delay in a Logic Gate
• Effort delay f = gh (stage effort)– Has two components
• g: logical effort– Measures relative ability of gate to deliver current– g 1 for inverter
• h: electrical effort = Cout / Cin
– Ratio of output to input capacitance– Sometimes called fanout
• Parasitic delay p– Represents delay of gate driving no load– Set by internal parasitic capacitance
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Delay Plots
d = f + p = gh + p
Electrical Effort:h = C
out / C
in
Nor
mal
ized
Del
ay: d
Inverter2-inputNAND
g = 1p = 1d = h + 1
g = 4/3p = 2d = (4/3)h + 2
Effort Delay: f
Parasitic Delay: p
0 1 2 3 4 5
0
1
2
3
4
5
6
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Computing Logical Effort
• DEF: Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current.
• Measure from delay vs. fanout plots• Or estimate by counting transistor widths
A YA
B
YA
BY
1
2
1 1
2 2
2
2
4
4
Cin = 3g = 3/3
Cin = 4g = 4/3
Cin = 5g = 5/3
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Catalog of Gates• Logical effort of common gates
Gate type Inputs
1 2 3 4 n
Inverter 1
NAND 4/3 5/3 6/3 (n+2)/3
NOR 5/3 7/3 9/3 (2n+1)/3
Tristate-mux 2 2 2 2 2
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Catalog of Gates
Gate type Number of inputs
1 2 3 4 n
Inverter 1
NAND 2 3 4 n
NOR 2 3 4 n
Tristate / mux
2 4 6 8 2n
Parasitic delay of common gatesIn multiples of pinv (1)
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Example: Ring Oscillator
Estimate the frequency of an N-stage ring oscillator
Logical Effort: g = 1Electrical Effort: h = 1Parasitic Delay: p = 1Stage Delay: d = 2Frequency: fosc = 1/(2*N*d) =1/4N
31 stage ring oscillator in 0.6 mm process has frequency of ~ 200 MHz
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Example: FO4 Inverter
Estimate the delay of a fanout-of-4 (FO4) inverter
Logical Effort: g = Electrical Effort: h =Parasitic Delay: p =Stage Delay: d =
d
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Example: FO4 Inverter
dEstimate the delay of a fanout-of-4 (FO4) inverter
Logical Effort: g = 1Electrical Effort: h = 4parasitic Delay: p = 1Stage Delay: d = 5
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Multistage Logic Networks
10x y z
20g1 = 1h
1 = x/10
g2 = 5/3h
2 = y/x
g3 = 4/3h
3 = z/y
g4 = 1h
4 = 20/z
out-path
in-path
CH
C
iG g
i i iF f g h
Logical effort generalizes to multistage networks
Path Logical Effort
Path Electrical Effort
Path Effort
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Paths that Branch
Is it possible write F=GH?No! Consider paths that branch:
G = 1H = 90 / 5 = 18GH = 18h1 = (15 +15) / 5 = 6h2 = 90 / 15 = 6F = g1g2h1h2 = 36 = 2GH
5
15
1590
90
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Branching Effort
on path off path
on path
C Cb
C
iB b
Introduce branching effortAccounts for branching between stages in path
Now we compute the path effortF = GBH
ih BH
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Designing Fast Circuits
i FD d D P
1ˆ Ni if g h F
1ND NF P
•Delay is smallest when each stage bears same effort
•Thus minimum delay of N stage path is
•This is a key result of logical effort Find fastest possible delay Doesn’t require calculating gate sizes
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Gate Sizes
• How wide should the gates be for least delay?
• Working backward, apply capacitance transformation to find input capacitance of each gate given load it drives.
• Check work by verifying input cap spec is met.
ˆ
ˆ
out
in
i
i
CC
i outin
f gh g
g CC
f
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Example: 3-stage path
• Select gate sizes x and y for least delay from A to B
8 x
x
x
y
y
45
45
A
B
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Example: 3-stage path
8 x
x
x
y
y
45
45
A
B
Logical Effort G = Electrical Effort H =Branching Effort B =Path Effort F =Best Stage EffortParasitic Delay P =Delay D =
f̂
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Example: 3-stage path
8 x
x
x
y
y
45
45
A
B
Logical effort G = (4/3)*(5/3)*(5/3) = 100/27Electrical Effort H = 45/8Branching Effort B = 3 * 2 = 6Path Effort F = GBH = 125Best Stage EffortParasitic Delay P = 2 + 3 + 2 = 7Delay D = 3*5 + 7 = 22 = 4.4 FO4
3ˆ 5f F
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Example: 3-stage path
• Work backward for sizes
y =
x =
8 x
x
x
y
y
45
45
A
B
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Example: 3-stage path
• Work backward for sizes
y = 45 * (5/3) / 5 = 15
x = (15*2) * (5/3) / 5 = 10
8 x
x
x
y
y
45
45
A
B
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Best Number of Stages
• How many stages should a path use?– Minimizing number of stages is not always fastest
• Example: drive 64-bit datapath with unit inverter
D =
1 1 1 1
64 64 64 64
Initial Driver
Datapath Load
N:f:D:
1 2 3 4
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Best Number of Stages• How many stages should a path use?
– Minimizing number of stages is not always fastest• Example: drive 64-bit datapath with unit inverter
D = NF1/N + P= N(64)1/N + N
1 1 1 1
8 4
16 8
2.8
23
64 64 64 64
Initial Driver
Datapath Load
N:f:D:
16465
2818
3415
42.815.3
Fastest
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Derivation
• Consider adding inverters to end of path
– How many give least delay?
• Define best stage effort
11
11
N
n
i invi
D NF p N n p
N - n
1 Extra Inverters
Logic Block:n
1 Stages
Path Effort F
1 1 1
ln 0N N Ninv
DF F F p
N
1NF
1 ln 0invp
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Best Stage Effort
1 ln 0invp
has no closed-form solution
Neglecting parasitics (pinv = 0), we find ρ= 2.718 (e)
For pinv = 1, solve numerically for ρ = 3.59
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Sensitivity Analysis
• How sensitive is delay to using exactly the best number of stages?
• 2.4 < < 6 gives delay within 15% of optimal– We can be sloppy!– I like = 4
1.0
1.2
1.4
1.6
1.0 2.00.5 1.40.7
N / N
1.151.26
1.51
( =2.4)(=6)
D(N
) /D
(N)
0.0
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Review of Definitions
Term Stage Pathnumber of stages l Nlogical effort gelectrical effort
branching effort
effort
effort delay fparasitic delay p
delay d=f+P
iG gout
in
CCh out-path
in-path
C
CH
on-path off-path
on-path
C C
Cb iB b
f gh F GBH
F iD fiP p
i FD d D P
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Method of Logical Effort
1) Compute path effort
2) Estimate best number of stages
3) Sketch path with N stages
4) Estimate least delay
5) Determine best stage effort
6) Find gate sizes
F GBH
4logN F
1ND NF P
1ˆ Nf F
ˆi
i
i outin
g CC
f
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Limits of Logical Effort
• Chicken and egg problem– Need path to compute G– But don’t know number of stages without G
• Simplistic delay model– Neglects input rise time effects
• Interconnect– Iteration required in designs with wire
• Maximum speed only– Not minimum area/power for constrained delay
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Summary
• Logical effort is useful for thinking of delay in circuits– Numeric logical effort characterizes gates– NANDs are faster than NORs in CMOS– Paths are fastest when effort delays are ~4– Path delay is weakly sensitive to stages, sizes– But using fewer stages doesn’t mean faster paths– Delay of path is about log4F FO4 inverter delays– Inverters and NAND2 best for driving large caps
• Provides language for discussing fast circuits– But requires practice to master